Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, determining whether the iterative decoding is suffering an impairment, and terminating the iterative decoding responsive to the determination of the impairment, otherwise continuing the iterative decoding to provide the decoded signal.

Abstract: In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.

Abstract: In one embodiment, a receiver includes parallel paths for signal channel processing and image channel processing. The paths may include a mixer to receive an intermediate frequency (IF) signal and to downconvert the IF signal to a channel baseband signal, a filter to generate a filtered channel value, a combiner to combine the channel baseband signal with a filtered channel value from the other path to obtain a channel path output, in addition to one or more controllers to generate a step control signal and update a weighting of the filters based at least in part on the step control signal.

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

Abstract: In one implementation, a receiver may have an analog front end with an amplifier to receive a radio frequency (RF) signal and a mixer to downconvert the signal to a baseband signal. Then, a demodulator may receive the baseband signal and obtain an audio signal therefrom. Still further, a controller may be coupled to receive a control signal corresponding to a variable impedance level, and control a local oscillator coupled to the mixer responsive to the control signal. The variable impedance may be controlled by a user to tune to the channel.

Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.

Abstract: A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART is provided for digitally communicating with an off-chip UART, which off-chip UART has an independent time reference, which communication between the on-chip UART and the off-chip UART is effected without clock recovery. The on-chip UART has a time-base derived from the temperature compensated clock. The temperature compensated clock provides a time reference for both the processing circuitry and the on-chip UART.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankets may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured.

Abstract: Microshells including a perforated pre-sealing layer and an integrated getter layer are provided. The integrated getter layer may be disposed between other layers of a perforated pre-sealing layer. The perforated pre-sealing layer may include at least one perforation, and a sealing layer may be provided on the pre-sealing layer to close the perforation.

Abstract: In one form, a keypad includes a substrate and a flexible membrane disposed above a top surface of the substrate. The substrate has the top surface, a first conductor below the top surface, an insulator layer separating the first conductor from the top surface, and a second conductor disposed in proximity to the first conductor and to the top surface and coupled to a voltage terminal. The flexible membrane is disposed above the top surface of the substrate and has a third conductor forming a key. The third conductor is movable relative to the top surface. In another form, a keypad system includes such a keypad and a capacitive sensing circuit coupled to the first conductor for sensing a change in capacitance between the first conductor and the voltage terminal when the third conductor moves relative to the top surface.

Abstract: A communications device is provided. The communications device includes a first antenna port coupled to a signal line, transmitter circuitry coupled to the signal line and configured to broadcast a radio frequency (RF) output signal across the first antenna port, tuning circuitry coupled to the signal line, and a controller configured to adjust a tuning of the tuning circuitry. The first antenna port, the transmitter circuitry, the tuning circuitry, and the controller are at least partially integrated on the same integrated circuit.

Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.

Abstract: An LCD controller includes at least one I/O pad for providing an LCD drive voltage in an LCD mode of operation. I/O pad logic drives the at least one I/O pad responsive to a provided bias voltage. Voltage selection logic selects a higher voltage between an LCD drive voltage and an externally provided system voltage as a first voltage. Bias voltage logic selects one of the system voltage or the first voltage as the bias voltage for the I/O pad logic. The system voltage is selected as the bias voltage for the I/O pad logic in a non-LCD mode of operation for the I/O pad and the first voltage is selected for the bias voltage for the I/O pad logic in the LCD mode of operation for the I/O pad.

Abstract: According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data.

Abstract: According to one embodiment, a method for updating filter values of an image canceller is provided. The method may include determining a channel-to-image (C/I) ratio between a channel signal and an image signal at the canceller input and generating a gain control value based at least in part on the C/I ratio. Then correlations between the channel signal and the image signal at the canceller's input and output can be generated, along with a gear control value based at least in part on a ratio between the correlations. In turn, one or more filters of the canceller can be updated using the control values.

Abstract: In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators.

Abstract: A radio receiver has a multipath equalizer that includes a filter and a coefficient estimator. The filter provides a reconstructed signal by applying a transfer function including a reflection coefficient and a delay coefficient to a multipath radio signal. The coefficient estimator adapts the reflection coefficient and the delay coefficient in response to a deviation in magnitude of the reconstructed signal from a normalized value. In one form, the filter evaluates the transfer function by truncating it to eight terms. In another form, the filter includes a delay line having delay elements for storing samples of the multipath radio signal received both before and after a current sample. In yet another form, the multipath equalizer further includes a normalizer that receives the multipath radio signal and provides a normalized multipath radio signal having a normalized magnitude to an input of the filter.

Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

Abstract: In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.