Patents Assigned to Silicon Motion, Inc. (TW)
  • Patent number: 12254219
    Abstract: A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 18, 2025
    Assignee: SILICON MOTION, INC.
    Inventors: Hsu-Ping Ou, Kuang-Ting Tai
  • Patent number: 12253564
    Abstract: An electronic device includes a functional circuit, a test mode circuit, and a verification circuit. The verification circuit generates and outputs the test waveform signals into the test mode circuit based on a clock signal provided from the test mode circuit, receives test result waveform signals from the test mode circuit when at least one test operation corresponding to the test pattern signal is performed, and compares the test result waveform signals with target result waveform signals to generate and output a failure result signal into the test mode circuit; the failure result signal is used to indicate whether at least one test bit failure occurs.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: March 18, 2025
    Assignee: Silicon Motion, Inc.
    Inventor: Tse-Yen Liu
  • Patent number: 12253957
    Abstract: A method of handling trim commands in a flash memory is provided. The method comprises: receiving a trim command; modifying logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command; and storing trim information of the trim command into one of data blocks of the flash memory after modifying the L2P address mapping entries according to the trim command.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: March 18, 2025
    Assignee: Silicon Motion, Inc.
    Inventor: Tzu-Yi Yang
  • Publication number: 20250085893
    Abstract: A method for performing data access control of a memory device and associated apparatus are provided.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 13, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: FAHAO LI
  • Publication number: 20250085892
    Abstract: A method for performing data access control of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access including data reading on the NV memory according to the plurality of host commands; and performing a reading parameter learning procedure to generate predicted data of a predicted reading voltage parameter offset regarding adjustment of a reading voltage parameter, for maintaining correctness of the data reading, for example: scanning for a best value, and adding latest information comprising the best value into a data set among one or more data sets in at least one reading-voltage control database; performing local linear regression according to the data set to update a reading voltage prediction function corresponding to a reading voltage prediction model; and generating or updating the predicted data according to the reading voltage prediction function.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 13, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: FAHAO LI
  • Patent number: 12249385
    Abstract: A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: March 11, 2025
    Assignee: Silicon Motion, Inc.
    Inventor: Fu-Jen Shih
  • Publication number: 20250078936
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read the first logical page to obtain first readout information, second readout information and third readout information, respectively; selecting a second logical page of the physical page; using a second set of threshold voltage to read the second logical page to generate fourth readout information; adjusting the first set of threshold voltages to generate an adjusted first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information; and using the adjusted first set of threshold voltages to read the first logical page of the flash memory module.
    Type: Application
    Filed: August 20, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20250077350
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.
    Type: Application
    Filed: August 20, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20250077085
    Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.
    Type: Application
    Filed: August 20, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20250077344
    Abstract: A flash memory controller, to be coupled between a host and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host to form a super block stored within the flash memory module, to generate wordline-dimensional check code data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional check code data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional check code data and the finger-dimensional check code data so as to obtain correct data content of the specific data.
    Type: Application
    Filed: August 20, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20250077346
    Abstract: A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.
    Type: Application
    Filed: August 19, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20250077343
    Abstract: The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.
    Type: Application
    Filed: June 2, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tzu-Yi Yang
  • Publication number: 20250077418
    Abstract: A control method of a memory device includes: reading and decoding first data of a first chunk, wherein the first chunk is located in a first data page of a super data page, and the super data page includes multiple data pages respectively located in multiple data planes; in response to the first chunk failing to be decoded, obtaining data of multiple corresponding chunks of the first chunk, wherein the multiple corresponding chunks are located in other data pages of the super data page; and in response to all of the data in the multiple corresponding chunks not being successfully decoded, determining whether to give up the decoding operation of the first chunk according to a symptom weight of the first chunk and at least one symptom weight of at least one corresponding chunk.
    Type: Application
    Filed: August 20, 2024
    Publication date: March 6, 2025
    Applicant: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 12242360
    Abstract: A method for performing data access management of a memory device in predetermined communications architecture to enhance sudden power off recovery (SPOR) of page-group-based redundant array of independent disks (RAID) protection with aid of suspendible serial number and associated apparatus are provided. The method may include: utilizing the memory controller to write preceding data and metadata thereof into at least one set of preceding pages in a first active block to make the metadata carry at least one preceding serial number; writing dummy data and other metadata into at least one set of dummy pages in the first active block to make the other metadata carry at least one suspended serial number which is equal to a last serial number among the at least one preceding serial number; and utilizing the memory controller to write subsequent data and metadata thereof to make it carry at least one subsequent serial number.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: March 4, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chun-Ju Chen, Po-Ting Chen
  • Publication number: 20250068561
    Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of multi-table checking and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first command from a host device, wherein the first command indicates that reading first data at a first logical address is requested; checking at least one logical-to-physical (L2P) address mapping table to generate a first checking result and starting performing a first read operation according to the first checking result, and checking a temporary physical-to-logical (P2L) address mapping table corresponding to a first active block to generate a second checking result for selectively performing a second read operation according to the second checking result; and returning the first data to the host device, wherein the first data is read according to one of the first checking result and the second checking result.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Ting-Fong Hsu
  • Publication number: 20250068336
    Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The method may include: utilizing a memory controller to receive a set of first commands from a host device, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block; determining a selected table update size among multiple predetermined table update sizes according to at least one predetermined rule, wherein the multiple predetermined table update sizes represent multiple table entry counts, respectively; and updating at least one logical-to-physical address mapping table in the NV memory according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, for further data accessing.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Keng-Yuan Hsu, Po-Cheng Lai
  • Patent number: 12235721
    Abstract: A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: February 25, 2025
    Assignee: Silicon Motion, Inc.
    Inventor: Fu-Jen Shih
  • Patent number: 12236115
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Grant
    Filed: January 15, 2024
    Date of Patent: February 25, 2025
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Publication number: 20250061022
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Applicant: Silicon Motion, Inc
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong DU
  • Patent number: 12231146
    Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: February 18, 2025
    Assignee: Silicon Motion, Inc.
    Inventor: Duen-Yih Teng