Abstract: A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided.

Abstract: The present invention provides a method for controlling a flash memory module. The method includes: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block comprises multiple first blocks respectively located in the multiple dies; for each first block in the super block, determining a last successfully read page of the first block; determining a data weak region of the super block according to the last successfully read pages of the first blocks in the super block; and moving data in the weak data region to other regions of the super block or to another super block.

Abstract: The present invention provides a method for controlling a flash memory module. The flash memory module includes a plurality of dies, each die includes a plurality of blocks, each block includes a plurality of pages, and the method includes the steps of: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining whether the first block is a full block or a blank block; and if the first block is not the full block or the blank block, writing dummy data to the first block so that the first block becomes the full block; and erasing the plurality of first blocks in the super block, so that the plurality of first blocks become a plurality of blank blocks.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: A method for performing mapping table management of a memory device in a predetermined communications architecture with aid of table analysis and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; and in response to the first command, loading a local logical-to-physical (L2P) address mapping table from a non-volatile (NV) memory into a volatile memory within the memory controller to be a temporary L2P address mapping table, changing multiple L2P table entries in the temporary L2P address mapping table to be multiple updated L2P table entries in a group-by-group manner, rather than an entry-by-entry manner, and updating the local L2P address mapping table in the NV memory according to the multiple updated L2P table entries of the temporary L2P address mapping table.

Abstract: The invention relates to a method, and an apparatus for programming data into flash memory. The method includes: reading operating settings of a virtual carrier; setting a redundant array of independent disks (RAID) engine for driving the RAID engine to complete a designated encryption or encoding operation on first data associated with the virtual carrier when the operation settings indicate that the first data associated with the virtual carrier need to go through a mid-end processing stage; and sending a programming index to a data access engine for driving the data access engine to read a programming table from the SRAM, and program the second data associated with the virtual carrier into a designated address in a flash module when the operation settings indicate that the second data associated with the virtual carrier need to go through the back-end processing stage.

Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: The invention is related to an apparatus and a method for driving redundant array of independent disks (RAID) engine. The method, performed by a RAID controller in a RAID pre-processor, including: completing a driving operation for performing a series of physical-layer signal interactions with a RAID engine according to a driving value in the configuration register. The driving value corresponds to a command issued by a processing unit. The processing unit performs an operation irrelevant from an encoding or a decoding of a parity of a page group in parallel of the driving operation by the RAID controller in coordination with the RAID engine.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER).

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. All the first host data-update commands of the first queue are popped out and executed in response that the third logical address is the same as any first logical address. All the second host data-update commands of the second queue are popped out and executed in response that the third logical address is the same as any second logical address.

Abstract: The present invention provides a control method of the memory device. In the operation of the memory device, the soft information is compressed by a control circuit within the flash memory module, so that the second readout information including the compressed soft information transmitted by the flash memory module has much smaller data size. Therefore, the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Abstract: A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.

Abstract: A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Abstract: The invention introduces a method for performing operations to namespaces of a flash memory device, by a processing unit of a storage device, at least including the steps: receiving a cross-namespace data-movement command from a host, requesting to move user data of a first logical address of a first namespace to a second logical address of a second namespace; cutting first physical address information corresponding to the first logical address of a first logical-physical mapping table corresponding to the first namespace; and storing the first physical address information in an entry corresponding to a second logical address of a second logical-physical mapping table corresponding to the second namespace.

Abstract: A data programming method for a flash memory includes: writing a write data to a page buffer of the flash memory; encoding the write data to generate first parity data corresponding to the write data, and writing the first parity data to the page buffer; while generating the first parity data, performing an error detection based on the write data and the first parity data to produce an error detection result; and when the error detection result indicates that there is no error in the first parity data, issuing a program command to the flash memory to program the write data and the first parity data in the page buffer into a flash memory element of the flash memory.