Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for reading data with an optimization read voltage (RV) table. The method includes: determining one set of RVs for a designated memory-cell type according to a current environmental parameter of a NAND-flash module and content of the optimization RV table; and reading data on a page corresponding to the designated memory-cell type from the NAND-flash module with the set of RVs. The optimization RV table includes multiple records and each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.
Abstract: The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. A redundant first logical address is removed from a matched one of the first host data-update commands in response that the third logical address is the same as any first logical address. A redundant second logical address is removed from a matched one of the second host data-update commands in response that the third logical address is the same as any second logical address.
Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.
Abstract: A method used in a flash memory controller includes: using an error correction code (ECC) circuit to perform an ECC operation upon data of a block of a flash memory chip/die of a flash memory device to generate an ECC result; when the ECC result indicates a failure, storing an access task corresponding to the block into a specific buffer; and, controlling a voltage generator of the flash memory device through a specific communication interface to control at least one address decoder of the flash memory device to access the block of the flash memory chip/die again according to at least one threshold voltage level of the voltage generator after the access task has been temporarily stored in the specific buffer for a specific default time.
Abstract: A method for performing access control of a memory device with aid of interrupt management includes: utilizing a memory controller to receive a set of commands from a host device through a transmission interface circuit of the memory controller; and in response to the set of commands, utilizing the memory controller to perform a set of accessing operations upon a non-volatile (NV) memory for the host device, and return a single message-signaled interrupt (MSI) corresponding to the set of commands to the host device through the transmission interface circuit, for notifying the host device of completion of device side access control of the memory device regarding the set of commands, to allow the host device to complete host side access control of the host device regarding the set of commands.
Abstract: A method for performing garbage collection (GC) management of a memory device with aid of dedicated information control and associated apparatus are provided. The method may include: receiving at least one first command, and performing at least one accessing operation on a non-volatile (NV) memory according to the at least one first command; and executing a GC procedure to start performing GC on the NV memory, for example: dividing a memory region of a volatile memory into multiple sub-regions to be multiple dedicated memory regions; selecting multiple source blocks; comparing address mapping tables to generate and store valid-data location information in the multiple dedicated memory regions, respectively; and performing multiple GC operations according to the valid-data location information respectively stored in the multiple dedicated memory regions.
Abstract: A method for performing storage space management of a memory device with aid of dynamic block configuration includes: configuring at least one portion of blocks among a plurality of blocks to be multiple first blocks in a first region and multiple second blocks in a second region according to a first reserved block threshold; combining the multiple first blocks into a set of first superblocks in the first region; and combining at least one portion of second blocks among the multiple second blocks into a set of second superblocks in the second region, wherein the first reserved block threshold is less than a minimum non-damaged block count among respective non-damaged block counts of a plurality planes, for a memory controller to increase available storage capacity by increasing a ratio of a size of the second region to a size of the first region.
Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.
Abstract: A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, the flash memory device comprising an input/output (I/O) control circuit, a command register, an address register, a memory cell array at least having a first plane and a second plane which is different from the first plane, at least one address decoder, and a control circuit having a specific buffer, and the method comprises: buffering command information of a command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the command register; buffering address information of the command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the address register; and controlling the specific buffer storing a transmission history information of the specific communication interface.
Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: configuring the flash memory module to have a super block, wherein the super block comprises a plurality of blocks respectively located in a plurality of dies; encoding M data respectively to sequentially generate M temporary parities, wherein M is a positive integer greater than two; storing the M temporary parities into N areas of a buffer sequentially, wherein N is less than M, each of the N areas is only allowed to store one temporary parity, and a first part of the N areas is always used to store a portion temporary parities of the M temporary parities and their subsequent updated temporary parities; and generating M parities according to the M temporary parities, respectively, and writing the M parities into the super block.
Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array based on a smaller search range and to make the flash memory device determine whether the multiple page units are empty pages; the search range can be defined by a start page address stored in the flash memory device.
Abstract: The invention provides a method for accessing a flash memory module, wherein the method includes the steps of: classifying multiple read retry tables into at least a first group and a second group to establish a classifying and sorting table, wherein each of the multiple read retry tables records at least one reading voltage, and any two read retry tables do not have exactly the same reading voltage; selecting a first read retry table from the first group to read a page of a block of the flash memory module to generate first read data; and when a decoder fails to decode the first read data, selecting a second read retry table from the first group to read the page of the block of the flash memory module to generate second read data for the decoder to decode.
Abstract: The present invention provides a control method of a flash memory controller. By dividing a plurality of logical address to physical address mapping tables into multiple groups, establishing a group-to-physical address mapping table, a storage unit relationship table and a latest updated storage unit table to manage the flash memory controller, the times of loading the group-to-physical address mapping table into a buffer memory can be reduced, so as to improve the efficiency of the flash memory controller.
Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is coupled to the flash memory device through the specific communication interface, and used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array and to make the flash memory device determine whether the multiple page units are empty pages.
Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
Abstract: A flash memory controller of a storage device is coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit sends commands and data between the flash memory device and the processor The processor controls the I/O circuit to send a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array based on a smaller search range and to make the flash memory device determine whether the multiple page units are empty pages, the search range defined by a start page address stored in the flash memory device.
Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the debug injection command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.
Abstract: The present invention provides a control method of a flash memory controller is disclosed, wherein the flash memory controller is configured to access a flash memory module, and the control method comprising: allocating a memory space within a memory for storing data from the host device; dividing the memory space into a plurality of zone buffers, wherein each of the zone buffers is used to store data corresponding to one zone having an opened state; and for a first zone buffer of the plurality of zone buffers, controlling a first buffer and a second buffer within the first zone buffer to alternately store data of a first zone from the host device and write the data of the first zone to a zoned namespace of the flash memory module.
Abstract: A method for performing data access management of a memory device in predetermined communications architecture to enhance sudden power off recovery (SPOR) of page-group-based redundant array of independent disks (RAID) protection with aid of suspendible serial number and associated apparatus are provided. The method may include: utilizing the memory controller to write preceding data and metadata thereof into at least one set of preceding pages in a first active block to make the metadata carry at least one preceding serial number; writing dummy data and other metadata into at least one set of dummy pages in the first active block to make the other metadata carry at least one suspended serial number which is equal to a last serial number among the at least one preceding serial number; and utilizing the memory controller to write subsequent data and metadata thereof to make it carry at least one subsequent serial number.