Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing a checking operation to obtain a checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device; reading the target data and associated metadata from the NV memory, wherein a latest version of the L2P table is available in the RAM when reading the target data from the NV memory is performed; and checking whether a recorded logical address within the metadata and the logical address received from the host device are equivalent to each other, to control whether to send the target data to the host device.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed in a host side to include: obtaining a value of an extended device-specific data (Ext_CSD) register in a flash controller from the flash controller, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; and allocating space in a system memory as an HPA buffer, and storing a plurality of first logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller when the value of the Ext_CSD register comprises information indicating that an HPA function is supported, where each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device.

Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion of the flash memory module as a zoned namespace; and determining a number of blocks within each block according to a size of each zone and a size of each block within the flash memory module.

Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of the data register. When the data register includes a boundary-lock pattern or a special symbol, the boundary detector outputs a starting address that the boundary-lock pattern or the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Abstract: The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

Abstract: An efficient mapping information management technology for non-volatile memory is disclosed. When a host requests to access data of a first logical address, a microprocessor of a controller of the non-volatile memory loads a first sub-mapping table from the non-volatile memory to a volatile memory. The microprocessor loads hierarchical pointer tables related to the first logical address into the volatile memory. Among the hierarchical pointer tables, each higher-level pointer table lists non-volatile memory physical addresses of lower-level pointer tables. A non-volatile memory physical address of the first sub-mapping table is obtained from a first pointer table according to a first index, for the microprocessor to load the first sub-mapping table from the non-volatile memory into the volatile memory for mapping information of the first logical address, and the first pointer table is in the lowest level among the hierarchical pointer tables loaded in the volatile memory.

Abstract: The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Abstract: The present invention provides a server including a SSD, a first node and a second node, wherein the first node comprises a first processor and a first memory, and the second node comprises a second processor and a second memory. When the first processor receives data from another device via network, the first processor stores the data in the first memory, and the first processor further sends the data to the second node; when the second processor receives the data from the first node, the second processor stores the data in the second memory, and the second processor further sends a notification to the first node to inform that the data is successfully stored in the second memory; and after and only after the first processor receives the notification from the second node, the first processor starts to write the data into the SSD.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a time-management circuit. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the time-management circuit is configured to generate current time information. In the operations of the flash memory controller, when the microprocessor writes data into last pages of a specific block of the flash memory module, the microprocessor writes the time information generated by the time-management circuit into one of the last pages of the specific block.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.

Abstract: A method and apparatus for performing block management regarding a non-volatile memory are provided. The method includes: determining whether a first blank block belongs to a cold block group or a hot block group according to an erase count of the first blank block; in response to the first blank block belonging to the cold block group, selecting the first blank block from a plurality of blank blocks as a target block, for performing data writing; according to at least one characteristic parameter regarding first data to be written, determining whether the first data belongs to a cold data group or a hot data group; and in response to the first data belonging to the hot data group, writing the first data into the first blank block to use the first blank block as a data block of the first data.

Abstract: A plane selection method is provided, which is applied to a data storage medium including a plurality of planes, wherein each of the planes includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages which includes a plurality of data columns is divided into a plurality of chunks. The plane selection method includes steps of defining at least one data column having a largest number of error bits in a worst chunk as a bad column until a quantity of bad columns is used up, determining whether at least two planes are uncorrectable according to a distribution of the bad columns, and eliminating a record of the bad columns and banning a worse plane which had the most bad columns than other planes.

Abstract: The background update of a host-to-device mapping (H2F) table designed for an efficient space trimming technology of data storage devices is shown. A controller handles a target bit in a trimming bitmap (TBM) and updates the H2F table to store information regarding the trimming status of a trimming target which has a specific length and is marked by the target bit. The controller programs the starting logical address and trimming length of the trimming target into a cache area of the temporary storage device. After the target bit handling, the controller flushes a sub-table of the trimming bitmap that manages the target bit from the cache area into the non-volatile memory.

Abstract: The invention relates to a non-transitory computer program product, a method and an apparatus for managing garbage collection process. The non-transitory computer program product includes program code to: determine source blocks to be processed, wherein each source block includes an invalid page; program user data of valid pages in the source blocks, whose quantity is less than a total number of pages in one first-type physical block, into empty pages in a second-type physical block, wherein the total number of pages in one first-type physical block is greater than a total number of pages in one second-type physical block; and fill remaining empty pages in the second-type physical block with dummy values.

Abstract: A method for performing access management of a memory device with aid of a Universal Asynchronous Receiver-Transmitter (UART) connection and associated apparatus are provided. The method may include: utilizing a UART of a memory controller within the memory device to receive a set of intermediate commands corresponding to a set of operating commands through the UART connection between the memory device and a host device, wherein before sending the set of intermediate commands to the controller through the UART connection, the host device converts the set of operating commands into the set of intermediate commands; converting the set of intermediate commands into the set of operating commands according to a command mapping table; and accessing a non-volatile (NV) memory within the memory device with the set of operating commands for the host device, and sending a response to the host device through the UART connection.