Abstract: The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Abstract: A method used by a flash memory initialization device for writing boot up information into a memory device including a controller and a flash memory includes: generating the boot up information; generating N block indices by calling a random function based on a first seed; generating M page indices for each of the N block indices; combining the M page indices with each of the N block indices to generate M×N candidate row addresses; and writing the boot up information from the flash memory initialization device into the flash memory by controlling the controller to write the boot up information into M pages belonging to at least one block sequentially based on the M×N candidate row addresses.

Abstract: An electronic device and related control method are provided. The electronic device includes a first connection interface, configured to be electrically connected to a first host system through a first cable, and a second connection interface, configured to be electrically connected to a second host system through a second cable. The electronic device further includes a transmission control device having a first communication channel and a second communication channel, wherein the transmission control device provides operation functions for at least one of the first host system and the second host system according to a connection state. The electronic device further includes a data access device configured to receive data transmitted by the at least one host system, and a channel-detecting device, detecting the impedance information between one or both of the first connection interface and the second connection interface and the at least one host system.

Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

Abstract: An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into superblocks, wherein said superblocks respectively correspond to said block numbers; and recording total capacity of all superblocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all superblocks include said superblocks.

Abstract: An efficient control technology for non-volatile memory is shown. A controller selects the main source block from the non-volatile memory, wherein the main source block has a logical group amount exceeding a threshold amount. The controller selects a target logical group from the main source block, and collects data of the target logical group to a destination block provided by the non-volatile memory to reduce the logical group amount of the main source block.

Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables.

Abstract: A method and apparatus for performing node information exchange management of an all flash array (AFA) server are provided.

Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.

Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).

Abstract: A data accessing method using data protection with aid of an Advanced Encryption Standard (AES) processing circuit, and associated apparatus such as memory device, memory controller, and the AES processing circuit are provided. The data accessing method includes: utilizing the memory controller to start receiving first protected data corresponding to a read request from predetermined storage space; utilizing the AES processing circuit to start performing decryption processing on the first protected data to obtain decrypted data; utilizing the AES processing circuit to start performing encryption processing on other data to obtain encrypted data to be second protected data corresponding to a write request; and utilizing the memory controller to start sending the second protected data to the predetermined storage space, for storing the second protected data into the predetermined storage space. The AES processing circuit can perform encryption and decryption simultaneously.

Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.

Abstract: A storage apparatus managing method applied to a first storage apparatus and a second storage apparatus coupled to the electronic apparatus is disclosed. The first storage apparatus includes a local registering region and a global registering region. The storage apparatus managing method includes: when the global registering region does not have a target data unit, reading the target data unit from the local registering region or from the second storage apparatus; and copying the target data unit to the global registering region. When the target data unit is copied to the global registering region, the target data unit is copied to a global registering buffer region, or otherwise in response to the global registering buffer region not having enough space, the target data unit is copied to a global registering file region.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method includes the steps of: sending a read command to the flash memory module to ask for data on at least one memory unit; receiving multi-bit information of a plurality of memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the plurality of memory cells to obtain a threshold voltage distribution of the plurality of memory cells for determining a decoding process.

Abstract: A method for performing data-accessing management in a storage server and associated apparatus such as a host device, a storage device, etc. are provided. The method includes: in response to a client request of writing a first set of data into the storage server, utilizing the host device within the storage server to trigger broadcasting an internal request corresponding to the client request toward each storage device of a plurality of storage devices within the storage server; and in response to the internal request corresponding to the client request, utilizing said each storage device of the plurality of storage devices to search for the first set of data in said each storage device to determine whether the first set of data has been stored in any storage device, for controlling the storage server completing the client request without duplication of the first set of data within the storage server.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.

Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.

Abstract: A flash memory controller includes a read-only memory, a microprocessor and a buffer memory, wherein the buffer memory includes a data temporary storage area having continuous addresses. When the flash memory controller receives data from a host device, the microprocessor determines whether there is enough space between the last stored data in the data temporary storage area and an end address of the data temporary storage area to store the entire content of the data. If there is not enough space between the last stored data in the data temporary storage area and the end address to store the entire content of the data, the microprocessor directly stores the data from a starting address in the data temporary storage area, without writing any part of the data to the area before the end address of the data temporary storage area.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory includes a plurality of data blocks. The micro-controller selects one of the data blocks as a source block and another one of the data blocks as a destination block. Also, the micro-controller duplicates data in the source block to the destination block, and when the data is corrupted and unrecoverable, stores an unrecoverable-error bit corresponding to the data into the destination block.