Abstract: The invention relates to a method, an apparatus and a computer program product for reading data from multiple flash dies. The method is performed by a processing unit when loading and executing program code to include: issuing a read instruction to a flash interface to drive the flash interface to activate a data read operation for reading data from a location in a die; calculating an output time point corresponding to the read instruction; and issuing a random out instruction corresponding to the read instruction to the flash interface to drive the flash interface to store the data in a random access memory (RAM) when a current time reaches to, or is later than the output time point.

Abstract: A method for performing adaptive locking range management, an associated data storage device and a controller thereof are provided. The method may include: receiving a security command from outside of the data storage device, wherein the security command is related to changing an old locking range into a new locking range; obtaining a start Logical Block Address (LBA) and a length value of the new locking range according to the security command; determining whether the start LBA of the new locking range is less than an end LBA of the old locking range, and determining whether an end LBA of the new locking range is greater than a start LBA of the old locking range; and in response to both determination results being true, performing data trimming on any respective non-overlapped portions of the new locking range and the old locking range.

Abstract: An access method is provided, which is applied to a memory device. The memory device is coupled to a host device, the host device is configured to provide a data, the memory device includes a SSD controller and a volatile memory, the volatile memory is coupled to the SSD controller, and the volatile memory includes a data storage area. The access method includes: the SSD controller receiving the data, the SSD controller generating a corresponding cyclic redundancy check code according to the data, and the SSD controller sequentially storing the data and the cyclic redundancy check code into the data storage area.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.

Abstract: A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory includes a first block and a second block, wherein the first block stores firmware code. The micro-controller writes one predetermined string into the second block before an execution of the firmware code, and determines whether there is more than one predetermined string in the second block. In response to there being no more than one predetermined string in the second block, the micro-controller allows the execution of the firmware code and erases the predetermined string in the second block upon successful completion of a prerequisite procedure during the execution of the firmware code. In response to there being more than one predetermined string in the second block, the micro-controller does not allow the execution of the firmware code.

Abstract: A method for performing access management of a memory device with aid of information arrangement and associated apparatus (e.g. the memory device and controller thereof, and an associated electronic device) are provided. The method may include: when the host device sends a write command to the memory device, utilizing the memory controller to generate a plurality of ECC chunks respectively corresponding to a plurality of sets of memory cells of the NV memory according to data, for establishing one-to-one mapping between the plurality of ECC chunks and the plurality of sets of memory cells; and utilizing the memory controller to store the plurality of ECC chunks into the plurality of sets of memory cells, respectively, to prevent any two ECC chunks of the ECC chunks from sharing a same set of memory cells of the sets of memory cells, to enhance read performance of the memory controller regarding the data.

Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: activate an eye-diagram analyzer to adjust a parameter of an equalizer according to magnitudes corresponding to an eye-diagram, which are generated by the eye-diagram analyzer, and repeatedly adjust a parameter of the equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state. The symbol decoding error is detected during a reception of host data from a host side according to a command issued by the host side, which is defined in Universal Flash Storage (UFS) specification.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is arranged to configure a plurality of first memory blocks to receive data from a host device. The first memory blocks form at least a first superblock. When an amount of data stored in the first memory blocks reaches a specific value, the memory controller moves the data from the first memory blocks to a plurality of second memory blocks in a predetermined procedure. The second memory blocks form at least a second superblock. The second superblock includes the second memory blocks located in different memory chips. The data stored in two adjacent logical pages in the first superblock is written in two second memory blocks located in different memory chips.

Abstract: A method for performing sudden power off recovery (SPOR) management, an associated memory device and a controller thereof, and an associated electronic device are provided. The method may include: triggering writing an expansion block; regarding a target block, setting a page count and a start page number for being processed with binary search; at least according to the page count and the start page number, performing the binary search on the target block to find a first empty page within the target block; performing page-by-page search, starting from the first empty page in a backward direction within the target block, to find the last valid page within the target block; determining an abandonment range within the expansion block according to the last valid page and the first empty page; and performing dummy programming on all expansion pages within the abandonment range.

Abstract: The invention introduces a non-transitory computer program product for handling a sudden power off recovery (SPOR) to include program code to: drive a flash access interface to read pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); mark the last correct page of the current block according to page read statuses for the current block; configure n1 pages after the next page of the last correct page of the current block as dummy pages; and drive the flash access interface to store data of the last correct page and its previous n2-1 pages of the current block in empty pages after the last dummy page of the current block, wherein any of n1 and n2 is a positive integer.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: repeatedly detecting whether a voltage supplied to the flash controller is lower than a first threshold; and issuing a program command to a flash module for programming data into the flash module and performing a supervision procedure when the voltage is lower than the first threshold. The supervision procedure includes steps for: repeatedly detecting whether the voltage is lower than a second threshold during a time period when issuing the program command to the flash module until transmitting the data to the flash module completely; and cancelling the program command when the voltage is lower than the second threshold.

Abstract: A data storage device and a method for sharing memory of controller thereof are provided. The data storage device comprises a non-volatile memory and a controller, which is electrically coupled to the non-volatile memory and comprises an access interface, a redundant array of independent disks (RAID) error correcting code (ECC) engine and a central processing unit (CPU). The CPU has a first memory for storing temporary data, the RAID ECC engine has a second memory, and the controller maps the unused memory space of the second memory to the first memory to be virtualized as part of the first memory when the second memory is not fully used so that the CPU can also use the unused memory space of the second memory to store the temporary data.

Abstract: A data erasing method of a non-volatile memory and a storage device using the same are provided. The data erasing method of the non-volatile memory includes the following steps. A boost circuit is boosted to output a damage voltage. A switch is turned on to apply the damage voltage to the non-volatile memory. The switch is connected between the boost circuit and the non-volatile memory. The non-volatile memory is destroyed by the damage voltage.

Abstract: An efficient control technology for non-volatile memory is shown. A non-volatile memory provides a storage space that is divided into blocks. When programming the write data issued by the host to the non-volatile memory, the programming order of the blocks is recorded. Garbage collection is based on the recorded programming order. Sequential data can be collected to the destination block in sequence.

Abstract: A method for selecting bad columns in a data storage medium is provided. The data storage medium is coupled to a control unit, and the data storage medium includes data blocks, wherein each of the data blocks includes columns. The columns are divided into chunks. The method for selecting bad columns in the data storage medium includes following steps. (a) The control unit calculates a number of bad columns in each of the chunks to sorts the chunks, wherein the bad columns are selected from the columns. (b) The control unit sequentially marks or records the bad columns in each of the chunks with bad column groups, wherein a bad column position and a bad column number in each of the chunks are marked or recorded in each of the bad column groups.

Abstract: An access device includes a memory controller coupled to a memory device and configured to access the memory device. The memory controller is further configured to perform a test procedure on the memory device to obtain a test result, write a boot code index, which indicates a predetermined address for storing predetermined system data of the memory device and a copy rule adopted for generating one or more duplicates of the predetermined system data, in the memory device, establish system data of the memory device according to the test result, write the system data into the predetermined address as the predetermined system data, and write the system data in one or more memory blocks of the memory device as the duplicates of the predetermined system data according to the copy rule.

Abstract: A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.