Abstract: A data storage device waking up from a sleep mode rapidly is disclosed. The data storage device uses a controller to operate a non-volatile memory. The controller has a microprocessor and a volatile memory. The microprocessor loads boot code from the non-volatile memory to a not-always-on area of the volatile memory according to a script loaded on an always-on area of the volatile memory. The microprocessor executes the boot code loaded on the not-always-on area to load an in-system program from the non-volatile memory to the not-always-on area for execution of the in-system program. The script loaded on the always-on area is loaded from the non-volatile memory, and the non-volatile memory is searched to load the script to the always-on area in response to powering on a data storage device containing the non-volatile memory from a power-off state.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side, at least including: in response to different types of host IO commands, using multiple stages of a generic framework to drive a frontend interface to interact with a host side for transmitting user data read from a storage unit to the host side, and receiving user data to be programmed into the storage unit from the host side.

Abstract: The invention introduces a method for controlling data access to a flash memory, performed by a processing unit, including steps of: obtaining a logical address associated with a data read operation; determining whether a group table corresponding to the logical address is queued in a locked queue, or a hot zone of a swap queue; and prohibiting content of the locked queue and the swap queue from being modified when the group table corresponding to the logical address is queued in the locked queue, or the hot zone of the swap queue.

Abstract: High performance data storage device is disclosed, which has a memory controller dynamically updating mapping information on the temporary storage to manage physical space information mapped to a logical address recognized by a host. The memory controller uses a first bit to an Nth bit of the physical space information to indicate a physical space of the non-volatile memory or a cache address of the data cache space, without using additional bits to map the physical space information to the non-volatile memory or the data cache space, where N is a number greater than one. Among numbers formed by the first to the Nth bit, the memory controller uses numbers corresponding to non-existent physical space of the non-volatile memory to map the physical space information to the non-volatile memory or the data cache space.

Abstract: A memory apparatus includes: a plurality of non-volatile (NV) memory elements each including a plurality of physical blocks; a volatile memory for storing a global page address linking table; a transmission interface, for receiving commands from a host; and a processing unit, for obtaining a first host address and first data from a first host command, and a second host address and second data from a second host command, linking the first host address to a first page of a physical block and storing the first data in the first page, and linking the second host address to a second page of the physical block and storing the second data in the second page to build a local page address linking table; wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: A mapping table updating method executable by a data storage device is provided. The data storage device includes a non-volatile memory and a controller. The mapping table updating method includes steps of: step A: configuring the controller to process a command issued by a host, and determine whether to trigger a partial garbage collection procedure when the command is a write command; when it is determined to trigger the partial garbage collection procedure, then performing step B: copying partial valid data in at least one source block to a destination block according to a segmentation condition; and step C: updating a logical-to-physical address mapping table of the data storage device according to a logical address of the copied partial valid data and a physical address in the destination block where the partial valid data is located, and returning to perform the step A.

Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: repeatedly adjust a parameter of an equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks include multiple table blocks configured to store tables and multiple data blocks configured to store data. The memory controller is configured to receive a predefined command which is a command from a host device to instruct the memory controller to perform initialization of the data storage device. The initialization of the data storage device includes a plurality of processing procedures which include a first portion of processing procedures and a second portion of processing procedures. The memory controller is configured to perform the first portion of processing procedures in response to the predefined command. After the first portion of processing procedures has been finished, the memory controller is configured to notify the host device that the data storage device is ready.

Abstract: The present invention provides a memory device including a connector and a flash memory controller. The connector is configured to connect to a first host and a second host. The flash memory controller is configured to select one of the first host and the second host based on a selection signal, and the flash memory controller only processes commands from the selected one of the first host and the second host, and accesses a flash memory module based on the commands.

Abstract: A flash memory controller is disclosed. The flash memory controller is configured to access a flash memory module, wherein the flash memory module includes a plurality of first blocks and a plurality of second blocks, and the flash memory controller includes a microprocessor and a read-only memory storing a program code. When the flash memory controller is powered on, when the flash memory controller is required to write data into the flash memory module, the microprocessor writes the data into the plurality of first blocks only; and the microprocessor writes subsequent data into the second blocks only when a quantity of the plurality of first blocks written by the flash memory controller after power on is greater than a threshold value.

Abstract: A method for performing programming management, associated memory device and a controller thereof are provided. The memory device may include a non-volatile (NV) memory, and the NV memory may include a plurality of NV memory elements. The method may include: before programming a target NV memory element of the plurality of NV memory elements, checking whether another NV memory element of the plurality of NV memory elements is in a busy state or in a non-busy state; and when the other NV memory element enters the non-busy state, programming the target NV memory element.

Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of dies, and each of the dies includes a first memory plane and a second memory plane, wherein each of the first memory plane and the second memory plane includes a plurality of physical pages. The controller retrieves data of a first physical page of the first memory plane and data of a second physical page of the second memory plane in response to a read command which is arranged to read a target page.

Abstract: The invention introduces a non-transitory computer program product for activating a flash device when executed by a processing unit of the flash device to have program code to: determine whether the flash device is physically reset when the flash device enters a test mode perform an operation of a first phase for transmitting a very first message to a card-initialization host when the flash device is physically reset; and perform an operation of a second phase for searching a flash module for information referenced by In-System Programming (ISP) code, obtaining the ISP code from a designated address, and programming the ISP code into the flash module when the flash device is not physically reset.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory block to receive data and records multiple logical addresses in a first mapping table. When the predetermined memory block is full, the memory controller edits a second mapping table based on the first mapping table. When editing the second mapping table, the memory controller determines whether M consecutive logical addresses have been recorded in the first mapping table. When the memory controller determines that M consecutive logical addresses have been recorded in the first mapping table, the memory controller edits the second mapping table according to a data compression rate (R), such that one or more fields, which correspond to one or more logical addresses recorded in the first mapping table, of the second mapping table are skipped and not edited. M and R are positive integers greater than 1.

Abstract: A high-performance data storage device is disclosed, including a non-volatile memory, a controller, and a temporary storage. Sub mapping tables divided from a logical-to-physical address mapping table according to logical address groups are stored in mapping blocks allocated in the non-volatile memory. The controller limits the number of mapping blocks by garbage collection, and performs garbage collection on a source mapping block in sections. During each garbage collection section, the controller downloads valid sub mapping tables from the source mapping block to the temporary storage and then programs the valid sub mapping tables from the temporary storage to a destination mapping block. The temporary storage is repeatedly used to store valid sub mapping tables downloaded in the different garbage collection sections.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.