Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory controller determines whether execution of a garbage collection procedure is required according to a number of spare memory blocks. When the execution of the garbage collection procedure is required, the memory controller determines an execution period according to a latest editing status of a plurality of open memory blocks; starts the execution of the garbage collection procedure so as to perform at least a portion of the garbage collection procedure in the execution period; and suspends the execution of the garbage collection procedure when the execution period has expired but the garbage collection procedure is not finished. The memory controller further determines a time interval for continuing the execution of the garbage collection procedure later according to the latest editing status of the open memory blocks.

Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.

Abstract: A multi-screen display control device is shown, in which a plurality of cards are connected in series through universal serial bus (USB) cables. Image data provided by a host is transferred through the USB cables. A first-stage card includes a plurality of first-stage graphics processing units (GPUs) and a first clock buffer. Based on the image data, the first-stage GPUs generate a plurality of high-definition multimedia interface (HDMI) sub-images to be displayed on a plurality of screens. Through the first clock buffer, a clock signal is replicated onto a plurality of paths to be transferred to the different first-stage GPUs and thereby identical clocks are applied to the different first-stage GPUs. Through the first clock buffer, the clock signal is further replicated onto a clock output path to be transferred to a clock output terminal of the first-stage card and thereby is coupled to a second-stage card.

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

Abstract: The invention relates to a method, a non-transitory computer program product, and an apparatus for managing data storage. The method performed by a flash controller includes: obtaining information indicating a subregion to be activated, where the subregion is associated with a logical block address (LBA) range; triggering a garbage collection (GC) process being performed in background to migrate user data of all the or a portion of the LBA range associated with the subregion to continuous physical addresses in a flash device; and updating content of a plurality of entries associated with the subregion according to migration results, where each entry includes information indicating which physical address that user data of a corresponding logical address is physically stored in the flash device.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: A method for using an electronic device to activate amass production software tool to initialize a memory device including a flash memory controller and a flash memory includes: using the mass production software tool to retrieve an encrypted configuration file included by the mass production software tool; decrypting the encrypted configuration file to generate a temporarily decrypted configuration file; comparing unique information of the electronic device with unique information recorded in the temporarily decrypted configuration file to determine whether the electronic device is valid/authorized; and performing a flash memory initialization operation upon the flash memory when the electronic device is valid/authorized.

Abstract: An optimized non-volatile memory operating method. A data storage device has a plurality of non-volatile memory spaces, a plurality of command queues, and a controller. The command queues are provided to correspond to the non-volatile memory spaces one on one. The controller adds task switching commands into the command queues. The non-volatile memory spaces are operated through the same channel. The sharing of the same channel between the non-volatile memory spaces is optimized by the task switching commands.

Abstract: A card activation device includes a first control unit and a central control unit. In response to a first control command, the central control unit provides first authentication data to the first control unit and the first control unit transmits the first authentication data to the data storage device. After the first authentication data is transmitted to the data storage device, the central control unit provides second authentication data to the first control unit and the first control unit transmits the second authentication data to the data storage device. After the second authentication data is transmitted to the data storage device, the card activation device enters a fully locked state and performs an authentication procedure for authenticating the data storage device. Before the data storage device has passed the authentication procedure, the central control unit is not allowed to transmit any data to the data storage device.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a first predetermined memory block which is an SLC memory block and a second predetermined memory block which is a MLC memory block as buffers to receive data. The memory controller determines to use which scheme to receive data in a predetermined period dynamically according to an amount of valid data stored in the memory device. When the memory controller determines to use a first scheme, the memory controller uses the first predetermined memory block to receive data. When the memory controller determines to use a second scheme, the memory controller uses the first predetermined memory block and the second predetermined memory block to receive data. When the memory controller determines to use a third scheme, the memory controller uses the second predetermined memory block to receive data.

Abstract: A method and apparatus for performing automatic power control in a memory device are provided. The method includes: during an initialization phase of the memory device, performing signal level detection on a reference clock request signal to determine whether the reference clock request signal is at a first predetermined voltage level or a second predetermined voltage level, for performing the automatic power control for the memory device, wherein the reference clock request signal is received through an IO pad; and according to a logic value carried by an input signal of a selective regulation circuit (SRC), performing selective power control to generate a secondary power voltage according to a main power voltage, wherein the selective power control makes the secondary power voltage be either equal to the main power voltage or a regulated voltage of the main power voltage in response to the logic value carried by the input signal.

Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side, at least including: in response to different types of host IO commands, using multiple stages of a generic framework to drive a frontend interface to interact with a host side for transmitting user data read from a storage unit to the host side, and receiving user data to be programmed into the storage unit from the host side. The frontend interface includes a register, and a data line coupled to the host side. The stages of the generic framework are used to access to the register of the frontend interface and operate the data line of the frontend interface to complete interactions with the host side.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash storage. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: receiving a host write command from a host side; determining whether the flash storage needs to enter a hibernate state based on at least information regarding a length of data that has been programmed into the flash storage and/or a quantity of host write commands that have been executed after executing the host write command; and instructing the flash storage to enter the hibernate state when the length of data and/or the quantity of host write command meets a triggering condition.

Abstract: The invention introduces a non-transitory computer program product for adjusting equalization when executed by a processing unit of a storage device. The non-transitory computer program product includes program code to: activate an eye-diagram analyzer to adjust a parameter of an equalizer according to magnitudes corresponding to an eye-diagram, which are generated by the eye-diagram analyzer, and repeatedly adjust a parameter of the equalizer after a symbol decoding error is detected until an adjustment failure is detected or successive waveforms output from the equalizer belong to an eye open state. The symbol decoding error is detected during a reception of host data from a host side according to a command issued by the host side, which is defined in Universal Flash Storage (UFS) specification.

Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of the data register. When the data register includes a boundary-lock pattern or a special symbol, the boundary detector outputs a starting address that the boundary-lock pattern or the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Abstract: The invention relates to a non-transitory computer program product, a method and an apparatus for managing garbage collection process. The non-transitory computer program product includes program code to: determine source blocks to be processed, wherein each source block includes an invalid page; program user data of valid pages in the source blocks, whose quantity is less than a total number of pages in one first-type physical block, into empty pages in a second-type physical block, wherein the total number of pages in one first-type physical block is greater than a total number of pages in one second-type physical block; and fill remaining empty pages in the second-type physical block with dummy values.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event The method, performed by a flash controller, includes steps for: repeatedly detecting whether a voltage supplied to the Hash controller is lower than a first threshold; and issuing a program command to a flash module for programming data into the flash module and performing a supervision procedure when the voltage is lower than the first threshold. The supervision procedure includes steps for: repeatedly detecting whether the voltage is lower than a second threshold during a time period when issuing the program command to the flash module until transmitting the data to the flash module completely; and cancelling the program command when the voltage is lower than the second threshold.