Abstract: A method for performing data-compression management in a storage server may include: receiving data from a host device; performing entropy detection on a plurality of sets of partial data to generate entropy detection values of the plurality of sets of partial data, respectively; classifying the plurality of sets of partial data according to the entropy detection values of the plurality of sets of partial data, respectively, to perform data compression on at least one portion of the plurality of sets of partial data through a plurality of data compression modules, respectively, wherein the plurality of data compression modules correspond to different compression capabilities, respectively; and storing the plurality of sets of partial data into at least one storage device of the storage server and recording address mapping information of the plurality of sets of partial data, respectively. An associated apparatus is also provided.

Abstract: A data storage device is provided. The data storage device includes a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory is configured to store a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables. The memory controller includes a first processing core and a second processing core. The first processing core receives a host access command from a host. When a specific G2P table corresponding to a specific logical address in the host access command is not stored in the DRAM, the first processing core determines whether the second processing core has loaded the specific G2P table from the flash memory to the DRAM according to the values in a first column in a first bit map and in a second column of a second bit map.

Abstract: The present invention discloses a method for accessing a flash memory module, wherein the flash memory module comprises a plurality of block, each block is implemented by a plurality of word lines, and each word line comprises a plurality of memory cells supporting a plurality of states. The method comprises the steps of: reading the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells; determining a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information; reading the memory cells of a second word line to obtain readout information of the second word line; and using the target decoding flow to decode the readout information of the second word line.

Abstract: An unbalanced plane management method, an associated data storage device and the controller thereof are provided. The unbalanced plane management method may include: setting an unbalanced plane number; selecting at least one plane with a plane count calculated by subtracting the unbalanced plane number from a maximum plane number, and recording at least one set of blocks of the at least one plane to a block skip table; according to block numbers as indexes, combining blocks of unselected planes into superblocks, wherein said superblocks respectively correspond to said block numbers; and recording total capacity of all superblocks and the unbalanced plane number, to generate a latest record of records of multiple types of storage capacity, for further setting storage capacity configuration of the data storage device, wherein said all superblocks include said superblocks.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory controller is coupled to the memory device and is configured to access the memory device. In a garbage collection procedure, the memory controller is configured to select multiple spare memory blocks as destination memory blocks and move valid data stored in at least one source memory block into the destination memory blocks. In the garbage collection procedure, the memory controller is further configured to determine an attribute of each valid data and determine which destination memory block to move the valid data into according to the corresponding attribute. Valid data having the same attribute is moved to the same destination memory block.

Abstract: A security extension design for non-volatile memory is shown. There is an in-system program loaded into the non-volatile memory. A memory controller downloads the in-system program to a data register to provide base firmware code, a function pointer structure and security firmware code on the data register. The memory controller executes the base firmware code, and security functions of the security firmware code are called by the base firmware code through information recorded in the function pointer structure and thereby the memory controller is switched to operate the non-volatile memory at a higher security level. The security firmware code uses an application programming interface (API) and is compatible with multiple projects.

Abstract: The invention introduces a non-transitory computer program product for scheduling execution of host commands when executed by a processing unit of a flash controller. Space of a random access memory of the flash controller is allocated for a first queue and a second queue, and the first queue stores the host commands issued by a host side in an order of time when the host commands arrive to the flash controller. The non-transitory computer program product includes program code to: migrate one or more host write commands from the top of the first queue to the second queue in an order of time when the host write commands arrive to the flash controller until the top of the first queue stores a host read command; fetch the host read command from the top of the first queue; execute the host read command to read user data from a flash module; and reply to the host side with the user data.

Abstract: High-efficiency control technology for non-volatile memory is shown. A controller allocates spare blocks of a non-volatile memory to provide a first active block and writes data issued by a host to the first active block. When the number of spare blocks is less than a threshold number and valid data of a first source block is less than a critical data amount, the controller uses the first active block as a data transfer destination for the valid data from the first source block.

Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.

Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings from a host. The controller determines whether the data out message will change the mode parameters which cannot be rewritten in the first mode page setting by performing bitwise logic operations on a new mode page setting in the data out message, preset values of the plurality of mode parameters of the first mode page setting, and a rewriteable setting for each bit of the first mode page setting.

Abstract: The invention introduces a method for producing solid state disk (SSD) devices, performed by a processing unit of a production host, to include steps of: loading a port-mapping configuration table including location information regarding each port connected to the production host; comparing location information in a hardware description file with the location information in the port-mapping configuration table to determine which ports that SSD devices are connected to; displaying a graphical user interface (GUI) on a displayer to indicate which ports are connected by SSD devices; and when an SSD device connected to one port that fails to activate, updating the GUI to display information indicating that an SSD device connected to the corresponding port that fails to activate.

Abstract: A method and apparatus for performing node information exchange management of an all flash array (AFA) server are provided. The method may include: utilizing a hardware manager module among multiple program modules running on any node of multiple nodes of the AFA server to control multiple hardware components in a hardware layer of the any node, for establishing a Board Management Controller (BMC) path between the any node and a remote node among the multiple nodes; utilizing at least two communications paths to exchange respective node information of the any node and the remote node, to control a high availability (HA) architecture of the AFA server according to the respective node information of the any node and the remote node, for continuously providing a service to a user of the AFA server; and in response to malfunction of any communications path, utilizing remaining communications path(s) to exchange the node information.

Abstract: A flash memory controller is configured to access a flash memory module, and the flash memory controller includes a read-only memory and a microprocessor. When the flash memory controller is powered on and performs an initialization operation, within a predetermined time range of the initialization operation, the microprocessor determines whether a number of spare blocks in the flash memory module is lower than a first threshold value to determine whether to perform a garbage collection operation. When an elapsed time since the flash memory controller is powered on exceeds the predetermined time range, the microprocessor determines whether a number of spare blocks in the flash memory module is lower than a second threshold to determine whether to perform another garbage collection operation, where the second threshold value is lower than the first threshold.

Abstract: A method for performing storage space management, an associated data storage device, and a controller thereof are provided. The method includes: receiving an identify controller command from a host device; in response to the identify controller command, returning a reply to the host device to indicate that a plurality of logical block address (LBA) formats are supported, where the plurality of LBA formats are related to access of a non-volatile (NV) memory, and the plurality of LBA formats include a first LBA format and a second LBA format; receiving a first namespace (NS) management command from the host device; in response to the first NS management command, establishing a first NS adopting the first LBA format; receiving a second NS management command from the host device; and in response to the second NS management command, establishing a second NS adopting the second LBA format.

Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO). The pSLC blocks are reserved from being written any data in regular operations until the SPO is detected.

Abstract: The invention relates to a method, a non-transitory computer program product, and an apparatus for encrypting and decrypting physical-address information. The method includes: receiving a first read command requesting of the flash controller for first physical block addresses (PBAs) corresponding to a logical block address (LBA) range from a host side, wherein each first PBA indicates which physical address that user data of a first LBA of the LBA range is physically stored in a flash device; reading the first PBAs corresponding to the LBA range from the flash device; arranging the first PBAs into entries; encrypting content of each entry by using an encryption algorithm with an encryption parameter to obtain an encrypted entry; and delivering the encrypted entries to the host side.

Abstract: A flash memory initialization method executed by a flash memory initialization device to initialize a flash memory device having a flash memory and a flash memory controller includes: determining an acceptable maximum number N of candidate addresses; determining a number M of different capacity sizes; classifying the candidate addresses into M portions; determining a difference value between two address values of any two adjacent addresses among the m-th portion of candidate addresses; determining multiple address values of the m-th portion of candidate addresses according to the difference value; and determining actual addresses of the m-th portion of candidate addresses according to the multiple address values; and controlling the flash memory controller to write the boot up information into at least one storage location corresponding to at least one of the m-th portion of candidate addresses according to the actual addresses.

Abstract: A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory block to receive data and accordingly records multiple logical addresses in a first mapping table. When the predetermined memory block is full, the memory controller edits a second mapping table or a third mapping table based on the first mapping table. The memory controller determines whether the first mapping table has recorded logical addresses of a predetermined number of consecutive logical pages. If not, the memory controller edits the second mapping table. If so, the memory controller skips editing the second mapping table and edits the third mapping table instead, so as to record the mapping information of a predetermined logical page among the predetermined number of consecutive logical pages as representative mapping information in a corresponding field of the third mapping table.