Abstract: A non-volatile memory operated through multiple channels. The non-volatile memory includes a plurality of chip-enable-signal controlled areas, each containing a plurality of dies. Simultaneous operations on the different dies of at least one target chip-enable-signal controlled space corresponding to a target channel are allowed. The control unit scans the non-volatile memory to check the health status of the dies of the target chip-enable-signal controlled space to assign a plurality of logical enable signals of the target channel to correspond to the dies of the target chip-enable-signal controlled space.
Abstract: A data storage device including a flash memory and a controller. The controller performs a first read operation on the pages of a first block of a first block group, and performs a maintenance process to determine whether the first group read count of the first block group is greater than a read threshold when the first read operation is finished. The controller scans the blocks of the first block group to obtain a plurality of first error bit numbers when the first group read count is greater than the read threshold, and updates the block corresponding to the first error bit number that is greater than an error-bit threshold.
Abstract: A detection method applied to a storage device including transmitting a Devslp command to a signal pin of the storage device; pulling high the voltage level at a control pin of the storage device when a first response corresponding to the Devslp command is received to enable the storage device to enter a sleep mode; pulling low the voltage level at the control pin when a first predetermined period has elapsed; transmitting a Comwake signal to the signal pin; and determining that the sleep mode of the device under test meets a specification when the storage device receives a second response corresponding to the Comwake signal in a second predetermined period.
Abstract: A memory controller includes a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to an external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via an SRAM bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data in the internal memory device.
Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware. The firmware includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message from a host, arranged to rewrite a first mode page setting among the plurality of mode page settings. The controller determines whether the data out message will change the mode parameters which cannot be rewritten in the first mode page setting according to the data out message. When the data out message will change the mode parameters which cannot be rewritten in the first mode page setting, the controller replies to the host with an UPIU response message indicating a failure event.
Abstract: A data management method includes steps of: receiving a read command; reading a page containing target data from a non-volatile memory when the target data corresponding to the read command is stored in the non-volatile memory; determining whether a count of reading of the page is greater than a read threshold; and if false, storing at least one record of subsequent data into a first storage space of a data buffering storage device; or if true, storing the at least one record of subsequent data into a second storage space of the data buffering storage device. Both of the target data and the at least one record of subsequent data are stored in the page, and the target data and the at least one record of subsequent data have a sequential relationship in terms of data reading. Another data management method and a corresponding data storage device are also provided.
Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
Abstract: Optimized writing techniques for nonvolatile memory are presented. A microcontroller switches between a first writing mode and a second writing mode to write data to the nonvolatile memory. The switching between the first writing mode and the second writing mode depends on a first accumulated amount of data written to the nonvolatile memory in the first writing mode, or a number of spare blocks of the nonvolatile memory that is evaluated after a garbage collection procedure.
Abstract: A method for moving data internally, performed by a processing unit, including at least the following steps. The processing unit transmits partial copyback read commands to a storage sub-unit through an access interface, where each partial copyback read command is used to direct logic circuits of the storage sub-unit to store partial data of a page of the storage sub-unit in a designated location of a data buffer of the storage sub-unit. The processing unit further transmits a copyback write command to the storage sub-unit through the storage sub-unit for programming the data of the data buffer in a new page of the storage sub-unit.
Abstract: The present invention provides a data-storage device. The data-storage device includes a flash memory and a controller. The flash memory has a plurality of blocks and each of the blocks has a plurality of pages. The blocks include a plurality of bad blocks that are labeled as damaged. The controller selects one of the bad blocks as a test block, and reads the pages in the test block to determine whether the pages in the test block are damaged. When all the pages in the test block are undamaged, the controller labels the test block as a spare block.
Type:
Grant
Filed:
January 6, 2018
Date of Patent:
July 2, 2019
Assignee:
SILICON MOTION, INC.
Inventors:
Pin-Chang Liu, Tai-Yu Tsou, Yi-Ming Liu
Abstract: A page aligning method for a data storage device is provided. The data storage device includes a non-volatile memory and the page aligning method includes steps of: executing a system initialization on the non-volatile memory to obtain a remaining storage capacity; selecting a number from a lookup table as an initial storage capacity according to the remaining storage capacity and a lookup table; and referring the initial storage capacity as a fixed capacity in the data storage device and writing the initial storage capacity into the non-volatile memory. A lookup table generating method and the data storage device are also provided.
Abstract: A data storage method for a data storage device is provided. The data storage method includes steps of: determining whether a power drop/loss event occurs; when the power drop/loss event is determined to have occurred, recording a voltage level of a charge storage device, wherein the charge storage device provides power to the data storage device during the power drop/loss event; determining whether the charge storage device is operating normally according to the recorded voltage level of the charge storage device; and when the charge storage device is determined to be not operating normally, configuring the data storage device to enter a safe operation mode. A data storage device is also provided.
Abstract: A method for accessing a flash memory module includes: sequentially writing Nth?(N+K)th data to a plurality of flash memory chips of the flash memory module, and encoding the Nth?(N+K)th data to generate Nth?(N+K)th ECCs, respectively, where the Nth?(N+K)th ECCs are used to correct errors of the Nth?(N+K)th data, respectively, and N and K are positive integers; and writing the (N+K+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth?(N+K)th ECCs to generate the (N+K+1)th ECC.
Abstract: A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result.
Abstract: A method of decoding a received message includes: determining a weighting vector corresponding to at least one bit of the received message according to a syndrome and a parity check matrix; determining a bit state of the bit according to a bit value of the bit; changing the bit state according to the weighting vector and a flipping threshold, wherein a change range of the bit state is variable; and flipping the bit according to the bit state.
Abstract: A method for performing dynamic resource management in a memory device, the memory device, and a controller thereof are provided. The memory device includes a non-volatile (NV) memory, and the NV memory includes a plurality of NV memory elements. The method may include: storing a plurality of sets of physical region descriptor (PRD) information related to a plurality of host commands, respectively, and storing a plurality of intermediate PRDs respectively corresponding to the plurality of sets of PRD information into a first queue; obtaining an intermediate PRD of the plurality of intermediate PRDs from the first queue, and storing the intermediate PRD into a second queue; sending a command to the NV memory according to the intermediate PRD in the second queue to access data; and when an operation of accessing the data is successful, releasing the intermediate PRD from the second queue to the first queue.
Abstract: A data storage device includes a flash memory and a controller. The controller is coupled to the flash memory and includes a ROM which stores a boot code. In an initialization procedure of the data storage device, the controller does not access the flash memory and receives a debug code from an external device, and executes the boot code and the debug code to complete the initialization procedure.
Abstract: The data storage device includes a first memory having error correction capability, and a controller coupled to the first memory. The controller is configured to calculate an error count of the first memory. The controller is configured to report a message to a host when the controller determines that an alarm condition is satisfied. The alarm condition is related to the error count of the first memory and a threshold count.
Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller receives a read command arranged to read data from a host, determines a plurality of read tasks by analyzing the read command, and determines task time of each of the read tasks according to the number of the read tasks and an I/O latency time. In a first read task of the read tasks, the controller reads a part of the data and transmits the read part to the host, and executes a first maintenance process according to a predetermined condition, wherein the predetermined condition includes a remain time and the remain time is the task time minus the time spent by the first read task.
Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.