Patents Assigned to Silicon Motion, Inc.
  • Patent number: 10635726
    Abstract: A data processing circuit includes a condition input circuit and a search engine array. The condition input circuit receives and stores multiple search conditions corresponding to multiple data search tasks. The search engine array receives the search conditions and performs the data search tasks in a parallel manner according to the search conditions. The search engine array includes a storage medium and multiple search engines. The search condition(s) corresponding to one data search task is provided to one search engine and the search engine array accesses a random access memory to load the data stored in the random access memory into the storage medium. The search engines search the data stored in the storage medium according to the corresponding search condition(s) to perform the corresponding data search task, concurrently, and obtain a corresponding search result.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 28, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Jiyun-Wei Lin
  • Patent number: 10630425
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; sending a NAC (negative acknowledgement control) frame to the second side to inform the second side that the reception error is occurred for the first data each time the reception error is determined for the first descrambled data; and when a total number of occurrences of the reception errors reaches a predefined threshold, disabling the descrambler of the lowest layer.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yu-Da Chen
  • Patent number: 10628319
    Abstract: The invention introduces a method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Yang-Chih Shen, Che-Wei Hsu
  • Patent number: 10630316
    Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Patent number: 10630424
    Abstract: The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, at least including: descrambling first data from a second side via an enabled descrambler of a lowest layer; determining whether a reception error is occurred by continuously monitoring first descrambled data; and when the reception error is occurred, disabling the descrambler of the lowest layer and issuing a first request to the second side for directing the second side to disable a scrambler, thereby disabling the second side to protect second data to be transmitted to the first side by using a data scrambling technique.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Fu-Jen Shih
  • Patent number: 10621038
    Abstract: The present invention provides a decoding method of a flash memory controller, wherein the decoding method includes the steps of: reading first data from a flash memory module; decoding the first data, and recording at least one specific address of the flash memory module according to decoding results of the first data, wherein said at least one specific address corresponds to a bit having high reliability errors (HRE) of the first data; reading second data from the flash memory module; and decoding the second data according to said at least one specific address.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 14, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20200110701
    Abstract: A storage device and a cache area addressing method is disclosed. The storage device includes a memory module, a buffer, a memory controller, and a cache area addressing circuit. The buffer includes a cache area. The memory controller is coupled to the memory module and the buffer. The cache area addressing circuit is coupled to the memory controller and the buffer and configured to perform the followings. A logical address from the memory controller is received. Whether the logical address corresponds to a logical address interval of the cache area is determined. When the logical address corresponds to the logical address interval of the cache area, the logical address is mapped to a first physical address in the cache area according to a base address. Otherwise, the logical address is mapped to a second physical address in the buffer.
    Type: Application
    Filed: August 9, 2019
    Publication date: April 9, 2020
    Applicant: SILICON MOTION, INC.
    Inventor: Yi-Shou Jhang
  • Patent number: 10613932
    Abstract: A method for controlling operations of a memory device, the memory device and controller thereof, and an associated electronic device are provided. The method may include: transmitting a read command to a non-volatile (NV) memory to make the NV memory output a data stream; and utilizing a plurality of sub-circuits of a control logic circuit of the controller to perform parallel processing upon the data stream, respectively. Utilizing the sub-circuits to perform parallel processing upon the data stream may include: utilizing a randomizing/de-randomizing and error correction code (ECC) circuit to perform de-randomizing and ECC decoding according to the data stream, wherein this operation is related to initialization of the memory device; and utilizing an empty-page detection circuit to perform empty-page detection according to the data stream, wherein this operation is related to speeding up of the initialization of the memory device.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: April 7, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Mei-Yu Hsu
  • Patent number: 10606744
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: building a physical block recording table corresponding to a logical address to physical address (L2P) mapping table, wherein the physical block recording table records at least one block whose physical address is recorded in the L2P mapping table; and when a specific block within the flash memory module is under a garbage collection operation, for a data page of the specific block whose logical address is within the L2P mapping table, referring to the physical block recording table to determine if reading the L2P mapping table from the flash memory module or not, for determining the data page to be valid or invalid.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 31, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Ting-Fong Hsu, Po-Tsang Chen
  • Patent number: 10606761
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes: building a physical address to logical address (P2L) table; receiving a read command asking for a data within the flash memory module, wherein the read command includes a first logical address; if the P2L table does not include information associated with the first logical address, reading a logical address to physical address (L2P) table from the flash memory module, and searching a first physical address corresponding to the first logical address according to the L2P table, wherein the first physical address is used to read the data from the flash memory module; and using the P2L table to update the L2P table.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 31, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chun-Ju Chen
  • Patent number: 10599516
    Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10600491
    Abstract: A method for managing a plurality of data blocks of a data storage device includes steps of: reading a plurality of data pages in the data blocks which having valid data; updating a plurality of access counts of the data pages in the data blocks; determining whether an access count of the data block is greater than or equal to an access count threshold, wherein the access count of the data block is selected from one of the access counts of the data pages therein; and when the determination is positive, storing data in the data block into a spare data block of the data blocks. The access count threshold is updated when an erase count of the data block is determined to be greater than or equal to an erase count threshold. A method of data management for a data storage device is also provided.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 24, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Po-Sheng Chou, Huan-Jung Yeh
  • Patent number: 10592410
    Abstract: A data storage device includes a memory device and a controller. The memory device includes a first buffer, a second buffer, and a backup memory block. The first buffer is an MLC block and the second buffer is an SLC block. The controller is coupled to the memory device, receives a write command to write predetermined data in the memory device and determines whether the predetermined data has to be written into different buffers. When the controller determines that the predetermined data has to be written into different buffers, the controller writes a portion of the predetermined data that has been written in one or more predetermined pages of the first buffer into the backup memory block.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 17, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Wen-Sheng Lin, Yu-Da Chen
  • Patent number: 10592157
    Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. The memory blocks include single-level cell blocks and multiple-level cell blocks. The controller is coupled to the memory device. When the controller executes a predetermined procedure to write data stored in the single-level cell blocks into the multiple-level cell blocks, the controller is configured to determine whether a valid page count corresponding to each single-level cell block is greater than a threshold, and when the valid page count corresponding to more than one single-level cell block is greater than the threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 17, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Wen-Sheng Lin, Yu-Da Chen
  • Patent number: 10592143
    Abstract: A method of data writing for a data storage device includes steps of: determining whether an event of power drop/loss is recorded, wherein the event of power drop/loss is associated with a power supplied by an external device; when it is determined that the event of power drop/loss is recorded, determining whether a backup power source operates abnormally; and when it is determined that the backup power source operates abnormally, the data storage device enters from a normal mode into a write through mode, wherein in the write through mode, data from the external device is written into a buffer area of the data storage device. A data storage device is also provided.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 17, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Tsai-Fa Liu, Hung-Lian Lien
  • Patent number: 10592412
    Abstract: A data storage device for dynamically executing the garbage-collection process is provided which includes a flash memory and a controller. The flash memory includes a plurality of blocks wherein each of the blocks includes a plurality of pages. The controller is coupled to the flash memory and is utilized to execute the garbage-collection process on the flash memory according to a number of at least one spare block in the flash memory and the number of non-spare blocks corresponding to different ratios of effective pages. The garbage-collection process is utilized for merging at least two non-spare blocks to release at least one spare block.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Kuan-Yu Ke
  • Patent number: 10579483
    Abstract: A data storage method includes steps of: selecting an active block to store data from a host; determining whether a power drop/loss event has occurred; when it is determined that a power drop/loss event has occurred, recording an index of the active block and an index of a last data-containing page in the active block; generating a primary F2H mapping table; and writing the primary F2H mapping table, the index of the active block and the index of the last data-containing page into a designated block. A data storage device and a data recovery program are also provided.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 3, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Yang-Chih Shen, Po-Sheng Chou
  • Patent number: 10579348
    Abstract: A data storage device utilized for confirming firmware data includes a flash memory and a controller. The controller is coupled to the flash memory to receive at least one first hash data related to a first firmware data, and it divides the first hash data into a plurality of data groups. The controller sorts the data groups based on a predetermined sorting mechanism to generate a first sorting hash data. The controller includes an efuse region for writing the predetermined sorting mechanism. When the controller determines that a second sorting hash data of a second firmware data is identical to the first sorting hash data or a second hash data of the second firmware data is identical to the first hash data, the second firmware data is allowed to update the controller.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 3, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Yao-Pang Chiang
  • Publication number: 20200064898
    Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.
    Type: Application
    Filed: January 31, 2019
    Publication date: February 27, 2020
    Applicant: Silicon Motion, Inc.
    Inventors: Chang-Wei SHEN, Te-Kai WANG, Pin-Hua CHEN
  • Patent number: 10574271
    Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 25, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Sheng-I Hsu