Abstract: The present invention discloses a storage device including a memory module and a memory controller. The memory controller includes a memory interface control unit, a command queue, a selecting unit, a buffer and a processing unit. The processing unit is configured to perform: generating a plurality of macro commands by combining a plurality of sequences of memory operation commands; writing the macro commands into the buffer; writing one or more than one operation parameter of the macro command corresponding to a host command into the buffer according to the host command outputted from a host; commanding the selecting unit to select the buffer as an input terminal; and commanding the buffer to output the macro command corresponding to the host command.

Abstract: A storage device including a volatile memory, a non-volatile memory and a controller is provided. The controller sends a plurality of commands to the non-volatile memory. When the controller receives a reset signal, the controller determines whether a specific operation has been completed. When the controller has not yet finished the specific operation, the controller continuously provides the commands to the non-volatile memory. When the controller has finished the specific operation, the controller performs a reset operation according to the reset signal.

Abstract: A method for creating a multi-namespace includes steps of: returning information of a namespace data structure according to a query command from, wherein the information of the namespace data structure comprises a maximum number and a total capacity of supportable namespace; receiving and determining whether a create command for creating a plurality of namespaces is correct, wherein the create command comprises a number of a namespace and a capacity of the namespace; and if the determination is correct, creating a global host logical-flash physical address (H2F) mapping table according to the create command, wherein a number of the global H2F mapping tables is independent of the maximum number of the supportable namespaces and the number of namespace. A method for accessing data in a multi-namespace is also provided.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

Abstract: A control unit for a data storage system is shown, which provides at least two buffers for updating mapping information through a host memory buffer HMB. A first buffer is provided for dynamic management of a physical-to-logical mapping table F2H that records a mapping relationship which maps a physical address within a target block to a logical address of a sector of user data stored at the physical address. The control unit performs reverse conversion on the mapping relationship to get reversed mapping information for the logical address and, accordingly, selects a target logical-to-physical mapping sub-table. A second buffer is provided to buffer the target logical-to-physical mapping sub-table when the target logical-to-physical mapping sub-table is read from the host memory buffer HMB. The control unit updates the target logical-to-physical mapping sub-table on the second buffer based on the reversed mapping information about the logical address.

Abstract: A host device coupled to a data storage device via a predetermined interface includes a processor and a thermal sensor. The thermal sensor senses ambient temperature to obtain a sensed temperature and provides the sensed temperature to the processor. When the processor determines that the sensed temperature is higher than a high-temperature threshold, the processor adjusts a data transfer speed of the predetermined interface according to a data processing speed required by subsequent data to be read from or written to the data storage device.

Abstract: A flash memory control technology with high reliability. In a power recovery process, a microcontroller is configured to duplicate a last write page of a run-time write block of a flash memory and thereby generate a duplicated page in the run-time write block to replace the last write page for reliability enhancement.

Abstract: A data storage device includes a memory device, an SRAM and a controller. The memory device includes a first buffer configured to store data of a plurality of consecutive logical pages. The SRAM stores a first mapping table. The first mapping table records which logical page the data stored in each physical page of the first buffer directs to. The controller is coupled to the memory device and the SRAM. When the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished. The predetermined number (M) is a positive integer greater than 1.

Abstract: A data storage device includes a memory device and a controller. The memory device includes at least an MLC block. The MLC block includes a plurality of physical pages. The controller is coupled to the memory device. When the controller determines that a sudden power-off has occurred during a previous write operation for writing data onto the MLC block, the controller finds a predetermined page that has been attacked by the sudden power-off, double programs the predetermined page and a first page that is directly related to the predetermined page and dummy programs a plurality of second pages that are indirectly related to the predetermined page.

Abstract: The invention introduces an apparatus for controlling data access that includes a memory, an access interface and a processing unit. The processing unit is arranged to operably receive logical-to-physical (L2P) mapping information corresponding to a programming operation through the access interface and store the L2P mapping information in the memory; searching the L2P mapping information to obtain a first logical address associated with user data stored in space of each physical address and a second logical address associated with user data stored in space of each next physical address; generating content of a plurality of entries of a link-based L2P mapping sub-table in the order of logical addresses, wherein each entry of the link-based L2P mapping sub-table stores information about a physical address and a second logical address associated with a corresponding first logical address; and store the link-based L2P mapping sub-table.

Abstract: The invention introduces an apparatus for searching linked lists at least including: a memory arranged to operably store a linked list; a linked-list search engine arranged to operably search content of the linked list until a search success or fail and generate a search result; and a processing unit arranged to operably write the content of the linked list into the memory, drive the linked-list search engine to start a search on the linked list and obtain the search result from the linked-list search engine.

Abstract: A data storage device includes a flash memory and a controller. The flash memory is utilized to store at least one data. The controller is coupled to the flash memory to receive at least one read command transmitted from a host, and reads the data stored by the flash memory according to the read command. The controller determines whether or not the length of the read command is greater than a first predetermined value. If the length is greater than the first predetermined value, the controller arranges the read command on a sequential queue. If the length is not greater than the first predetermined value, the controller arranges the read command on a random queue. The controller executes the read command of the random queue at high priority.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller writes the first data sector into a first physical page of the physical pages in response to a write command arranged to write a first data sector into a first logical page, records the mapping relationship of the first logical page and the first physical page in a first large-data-maintenance table and determines whether a small-data-maintenance table has a first data link of the first logical page when one of the large-data-maintenance tables is the first large-data-maintenance table corresponding to the first logical block and the first data sector is less than a predetermined length, and deletes the first data link of the small-data-maintenance table when the small-data-maintenance table has the first data link of the first logical page.

Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Abstract: A self-test method of a flash memory device includes: generating input data; encoding the input data to generate an error correction code; utilizing the input data and the error correction code to simulate to read a page of a flash memory of the flash memory device to generate soft information; and decoding the soft information to generate a decoding result.

Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.

Abstract: The invention introduces a method for performing operations to namespaces of a flash memory device, at least including the steps: receiving a namespace setting-update command from a host, requesting to update a namespace size of a namespace; determining whether the updated namespace size of the namespace can be supported; and when the updated namespace size of the namespace can be supported, updating a logical-physical mapping table of the namespace to enable the namespace to store user data of the updated namespace size.

Abstract: A high-security data center, having at least one data storage device, a host and an encryption and decryption key space. Each data storage device has a non-volatile memory and a controller chip. The controller chip includes an encryption and decryption module. The host machine operates the non-volatile memory via the controller chip. The encryption and decryption key space stores a key for the encryption and decryption module to perform data encryption and decryption. The encryption and decryption key space is isolated from the data storage device and the host machine by default so that a user who does not pass identity authentication is unable to operate the encryption and decryption module through the host to decrypt data of the non-volatile memory.