Patents Assigned to Siliconix Incorporated
  • Patent number: 10483356
    Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 19, 2019
    Assignee: SILICONIX INCORPORATED
    Inventors: Max Shih-kuan Chen, Hao-Che Chien, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, Gianluca Camuso
  • Publication number: 20190267456
    Abstract: A power semiconductor device and method for making same are disclosed. The device includes a source bonding pad and a drain bonding pad, a drain metallization structure including a drain field plate connected to the drain bonding pad, and a source metallization structure comprising a source field plate connected to the source bonding pad. At least a portion of at least one of the bonding pads is situated directly over an active area. A dimension of at least one of the field plates varies depending upon the structure adjacent to the field plate.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Applicant: SILICONIX INCORPORATED
    Inventors: Max Shih-kuan Chen, Hao-Che Chien, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, Gianluca Camuso
  • Patent number: 7795675
    Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: September 14, 2010
    Assignee: Siliconix Incorporated
    Inventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
  • Patent number: 7704836
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: April 27, 2010
    Assignee: Siliconix incorporated
    Inventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
  • Publication number: 20100019316
    Abstract: A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 28, 2010
    Applicant: Siliconix incorporated
    Inventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
  • Patent number: 7557409
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: July 7, 2009
    Assignee: Siliconix Incorporated
    Inventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
  • Patent number: 7435650
    Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: October 14, 2008
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi
  • Patent number: 7416947
    Abstract: A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: August 26, 2008
    Assignee: Siliconix incorporated
    Inventor: Mohamed N. Darwish
  • Publication number: 20080182376
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Application
    Filed: March 31, 2008
    Publication date: July 31, 2008
    Applicant: Siliconix incorporated
    Inventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
  • Patent number: 7394150
    Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: July 1, 2008
    Assignee: Siliconix incorporated
    Inventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
  • Patent number: 7326995
    Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: February 5, 2008
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, King Owyang
  • Patent number: 7291884
    Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: November 6, 2007
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi
  • Patent number: 7268032
    Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: September 11, 2007
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
  • Publication number: 20070187753
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Application
    Filed: January 26, 2007
    Publication date: August 16, 2007
    Applicant: Siliconix incorporated
    Inventors: Deva Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Lui, Kuo-In Chen, Sharon Shi
  • Patent number: 7238551
    Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: July 3, 2007
    Assignee: Siliconix incorporated
    Inventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
  • Patent number: 7233043
    Abstract: A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: June 19, 2007
    Assignee: Siliconix incorporated
    Inventor: Deva N. Pattanayak
  • Patent number: 7186609
    Abstract: A Schottky rectifier includes a rectifying interface between a semiconductor body and a metal layer. Trenches are formed in the surface of the semiconductor body and regions of a conductivity type opposite to the conductivity type of the body are formed along the sidewalls and bottoms of the trenches, the regions forming PN junctions with the rest of the body. When the rectifier is reverse-biased, the depletion regions along the PN junctions merge to occupy the entire width of the mesas. The device is fabricated by implanting dopant directly through the sidewalls and bottoms of the trenches, by filling the trenches with a material containing dopant and causing the dopant to diffuse through the sidewalls and bottoms of the trenches, or by implanting and diffusing the dopant into a gate filling material.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: March 6, 2007
    Assignee: Siliconix incorporated
    Inventors: Jacek Korec, Richard K. Williams
  • Patent number: 7183610
    Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 27, 2007
    Assignee: Siliconix incorporated
    Inventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
  • Patent number: 7118953
    Abstract: A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 10, 2006
    Assignee: Siliconix incorporated
    Inventor: Mohamed N. Darwish
  • Publication number: 20060121676
    Abstract: A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.
    Type: Application
    Filed: January 19, 2006
    Publication date: June 8, 2006
    Applicant: Siliconix incorporated
    Inventor: Mohamed Darwish