Abstract: A vertical DMOSFET includes a buried layer which is of the same conductivity type as the drain and which extends into the heavily doped substrate and approaches or extends to the surface of the epitaxial layer at a central location in the MOSFET cell that is defined by the body regions of the MOSFET. In some embodiments the upper boundary of the buried layer generally conforms to the shape of the body region, forming a dish shaped structure under the body region. A significant portion of the current flowing through the channel is drawn into the buried layer and since the buried layer represents a relatively low-resistance path, the total resistance of the MOSFET is lowered without any significant effect on the breakdown voltage. The conformal buried layer can be formed by implanting dopant into the epitaxial layer at a high energy (0.5 to 3 MeV). Before the implant, a thick oxide layer is formed in a central region of the MOSFET cell.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: A multiple integrated circuit intra-package configuration having a centrally mounted integrated circuit die and an additional circuit device mounted in the package periphery. The additional circuit device may provide multiple functions, for example, to protect and enhance the performance of the integrated circuit die. Examples of such functions are electrostatic discharge protection circuits and temperature sensing. The intra-package circuit device avoids problems such as simple and complex process compatibility and additional space requirements of utilizing components external to the package. The multiple circuit intra-package configuration utilizes the small space available in the vicinity of lead posts in integrated circuit packages such as SOIC and TSSOP configurations to mount circuit devices. In one embodiment, a circuit device, for example, a diode, is mounted on a lead post and connected as desired using any of a variety of connectability alternatives such as wire bonding.

Abstract: The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Abstract: An electrostatic discharge (ESD) protection circuit includes diodes connected in series back-to-back between the signal input and power supply terminals of the circuit to be protected. This allows the input signal to rise a selected distance above the supply voltage without triggering the ESD protection circuit. The ESD protection circuit can be fabricated in integrated form, with the diodes including a pair of P+ regions in an N-well or separate P+ regions forming PN junctions with separate N-wells. The diodes may also be formed in a layer of polysilicon over a field oxide region. Optionally, a second pair of back-to-back diodes can be connected between the signal input terminal and ground. This permits the input signal to fall a selected distance below ground without triggering the ESD protection circuit.

Abstract: The gate of a MOSFET is located in a lattice of trenches which define a plurality of cells. Most of the cells contain a MOSFET, but a selected number of the cells at predetermined locations in the lattice contain either a PN diode or a Schottky diode. The PN and Schottky diodes are connected in parallel with the channels in the MOSFET cells, with their anodes tied to the anode of the parasitic diodes in the MOSFET cells and their cathodes tied to the cathode of the parasitic diodes. When the MOSFET is biased in the normal direction (with the parasitic diode reverse-biased), the PN diodes provide a predictable breakdown voltage for the device and ensure that avalanche breakdown occurs at a location away from the trench gate where the hot carriers generated by the breakdown cannot damage the oxide layer which lines the walls of the trench. When the device is biased in the opposite direction, the Schottky diodes conduct and thereby limit charge storage at the PN junctions in the diode and MOSFET cells.

Abstract: A vertical N-channel trenched-gate power MOSFET includes an integral temperature detection diode. The diode includes an N+ region which serves as the cathode and which is formed within a tub of P-type material, which serves as the anode. The N+ region is separated from the trench. The anode of the temperature detection diode may be shorted to the source or may be separately biased. The temperature of the MOSFET is monitored by supplying a current through the diode in the forward direction and measuring the voltage across the forward-biased diode. In an alternative embodiment, a pair of N+ regions are formed within the P-tub, constituting a diode pair, and the temperature is detected by monitoring the difference in the voltages across the diodes. An overtemperature detection unit compares the voltage across the diode or diodes with a reference voltage and provides an output which can be used to turn the MOSFET off when the temperature reaches a predetermined level.

Abstract: The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Abstract: A four-terminal MOSFET, in which no combination of the source, drain, body and gate terminals are permanently connected together, is used as a synchronous rectifier capable of blocking an excessive current in a switching mode DC--DC converter resulting from a short-circuited load. In an N-channel version of the synchronous rectifier, the MOSFET body terminal is normally connected to the inductor in the DC--DC converter and is grounded when an overcurrent condition is detected. In a P-channel version of the synchronous rectifier, the MOSFET body terminal is normally connected to the converter output and is connected to the inductor when an overcurrent condition is detected. In addition, the voltage output by the inductor may be clamped using a zener diode or a snubber capacitor. A MOSFET body bias switching circuit is driven by overcurrent detection circuitry that may also be used to turn off the synchronous rectifier MOSFET gate.

Abstract: In a vertical trench MOSFET, a layer of increased dopant concentration is formed in a lightly-doped or "drift" region which separates the body region from the drain region of the MOSFET. The layer of increased dopant concentration denominated a "delta" layer, operates to spread out the current as it emerges from the channel of the MOSFET and thereby reduces the resistance of the MOSFET when it is turned on.

Abstract: A trenched-gate power MOSFET includes a body region that is formed within a mesa between adjacent gate trenches. The doping concentration of the body region is established such that the body region does not fully deplete at normal drain voltages. The MOSFET also includes a gate which is doped with material of a conductivity type opposite to that of the body. The width of the mesa and the doping concentration of the body region and gate are established such that the body region is fully depleted by the combined effects of the source-body and drain body junctions and the gate. As a result, the conventional source-body short can be eliminated, providing a greater cell packing density and lower on-resistance while maintaining acceptable levels of leakage current when the MOSFET is in the off-state.

Abstract: A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Pat. No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET.

Abstract: A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a PN junction diode that is connected in parallel with the channel region in each of the MOSFET cells. The diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. Several techniques can be used to adjust the breakdown voltage of the PN diode and to insure that breakdown occurs away from the sidewall of the trench, where it could cause impact ionization which could damage the gate oxide layer. According to one technique, a region of the epitaxial layer beneath the PN junction can be doped more heavily than the background level in the epitaxial layer to reduce the breakdown voltage of the PN junction diode. Also the radius of curvature of the PN junction and the separation between the protective diffusion and the heavily doped substrate can be used for this purpose.

Abstract: To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low R.sub.DSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed.

Abstract: A power MOSFET includes a pair of electrically isolated gates having different gate widths. The MOSFET is connected in a switching mode DC-DC converter, with the gates being driven by a pulse width modulation (PWM) control to vary the duty cycle of the gate drive signal and thereby regulate the output voltage of the DC-DC converter. In light load conditions, the larger gate is disconnected from the PWM control to reduce the gate capacitance which must be driven by the PWM control. In normal load conditions, the larger gate is connected to the PWM control to reduce the on-resistance of the MOSFET. Both of these operations increase the efficiency of the DC-DC converter.

Abstract: A frequency-to-current converter includes several capacitances with capacitive values that are effectively multiplied. After each of a series of periodic pulses, the voltage on a "ramp" capacitance is charged to a starting voltage. Then, during the period preceding the subsequent pulse, the ramp capacitance is allowed to discharge at a discharge rate that is a function of a voltage on a discharge-current bias capacitance. At the end of the period, the voltage on the ramp capacitance is sampled and compared to a reference. If the voltage on the ramp capacitance is too low or too high, indicating a discharge current that is too high or too low, respectively, the bias voltage on the bias capacitance is adjusted to compensate for the error. In another embodiment, a small ramp capacitance is repetitively charged and discharged between two reference voltage levels using alternating charge and discharge current levels.

Abstract: To reduce the distributed resistance in an integrated circuit die, a relatively thick metal strap layer is deposited on a bus or other conductive path in the top metal layer. The metal strap layer is formed by etching a longitudinal channel in the passivation layer over the bus and plating a thick metal layer, preferably nickel, in the channel. The metal strap layer dramatically reduces the resistance of the bus.

Abstract: A low voltage power MOSFET is disclosed which includes spaced apart base regions defining a conduction region therebetween. A highly doped region is provided adjacent the conduction region and is spaced from the base regions, being substantially equidistant thereto and extending therebelow. The spacing of the highly doped region from the base regions provides enhanced conductivity of the device and avoids the problem of device breakdown and punchthrough in regard to the source regions of the low voltage power device.

Abstract: A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions extending deeper than the trench) by providing a doped trench bottom implant region at the bottom of the trench and extending into the surrounding drift region. This trench bottom implant region has the same doping type, but is more highly doped, than the surrounding drift region. The trench bottom implant region significantly reduces the parasitic JFET resistance by optimizing the trench bottom implant dose, without creating reliability problems.

Abstract: An N-channel power MOSFET is fabricated with its source and body connected together and biased at a positive voltage with respect to its drain. The gate is controlled by a switch which alternately connects the gate to the source or to a voltage which turns the channel of the MOSFET fully on. When the gate is connected to the source, the device functions as a "pseudo-Schottky" diode which turns on at a lower voltage and provides a lower-resistance path than a conventional PN diode. When the gate is connected to the positive voltage the channel of the MOSFET is turned fully on. This MOSFET switch is particularly suitable for as a synchronous rectifier in a power converter where it reduces the power loss and stored charge in the "break before make" interval (i.e., the interval between the turn-off of the shunt switch and the turn-on of the synchronous rectifier).