Abstract: A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.

Abstract: A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.

Abstract: Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.

Abstract: A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

Abstract: A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A deep implanted N layer is formed below the trench at the interface between the substrate and the epitaxial layer, and N-type dopant is implant through the bottom of the trench to form an N region in the epitaxial layer below the trench but above and separated from the deep N layer. The structure is heated to cause the N layer to diffuse upward and the N region to diffuse downward. The diffusions merge to form a continuous N-type drain-drift region extending from the bottom of the trench to the substrate. Alternatively, the drain-drift region may be formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate.

Abstract: In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A portion of either a side wall of the trench or the bottom of the trench is implanted with an implant species. An insulating layer is then grown overlying the bottom and side wall of the trench. The implant species is selected such that the insulating layer grows more quickly on the bottom of the trench than on the side wall of the trench, resulting in a thicker insulating layer in the bottom of the trench than on the trench side walls.

Abstract: A trench MOSFET is formed by creating a trench in a semiconductor substrate, then forming a barrier layer over a portion of the side wall of the trench. A thick insulating layer is deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer deposits in the bottom of the trench at a faster rate than the thick insulating layer deposits on the barrier layer. Embodiments of the present invention avoid stress and reliability problems associated with thermal growth of insulating layers, and avoid problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract: A bidirectional battery disconnect switch, i.e., a switch which is capable of blocking a voltage in either direction when open and conducting a current in either direction when closed, is disclosed. The switch includes a four-terminal MOSFET having no source/body short and circuitry for assuring that the body is shorted to whichever of the source/drain terminals of the MOSFET is biased at a lower voltage.

Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

Abstract: Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.