Patents Assigned to SK hynix memory solutions inc.
  • Patent number: 9653176
    Abstract: Memory systems may include a memory including a plurality of memory blocks and a controller. The controller calculates an effective read disturb based on both a direct neighbor read disturb count and a non-direct neighbor read disturb count. The controller selects a wordline with the largest effective read disturb for test read and deciding whether to reclaim the data of the block based on the errors on the wordline.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 16, 2017
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Yu Cai, Fan Zhang, Haibo Li, June Lee
  • Patent number: 9653129
    Abstract: Apparatus for chip-to-chip communications may include a first driving unit and a second driving unit. The first driving unit may receive input data, generate a first output data based on the input data, and output the first output data. The second driving unit may receive the input data, generate a second output data with a pre-emphasis peak and output the second output data. The second output data may be generated by delaying and inverting the input data, and have a predetermined weight.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 16, 2017
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Chun-Ju Shen, Jenn-Gang Chern, Zichuan Cheng, Huei-Ching You
  • Patent number: 9607710
    Abstract: A read-threshold calibration method in a solid state storage system including measuring a threshold voltage distribution of solid state storage elements; determining a threshold voltage; decoding data according to the determined threshold voltage; filtering the threshold voltage distribution of solid state storage elements with a predetermined filter length when the decoding fails; changing the filter length; and repeating the determining, decoding, filtering, and changing steps with the changed filter length until the decoding is successful.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: March 28, 2017
    Assignee: SK hynix memory solutions Inc.
    Inventors: Fan Zhang, June Lee
  • Patent number: 9602111
    Abstract: An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 21, 2017
    Assignee: SK hynix memory solutions Inc.
    Inventors: Chun-Ju Shen, Jenn-Gang Chern
  • Patent number: 9569114
    Abstract: A write instruction includes a logical address and write data to be stored. An address mapping master is used to determine if the logical address is stored in an address table. A deduplication state is selected based at least in part on whether the logical address is stored in the address table and whether a fingerprint is stored in a fingerprint table. The fingerprint is generated using the write data. A fingerprinting slave is used to determine if the fingerprint is stored in the fingerprint table, where the address mapper and the fingerprinter are configured to run in parallel and the address mapper is the master to the fingerprinter's slave.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 14, 2017
    Assignee: SK hynix memory solutions Inc.
    Inventors: Indra G. Harijono, Zhenchuan Chai
  • Patent number: 9564239
    Abstract: A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: February 7, 2017
    Assignee: SK hynix memory solutions Inc.
    Inventors: Yu Cai, Johnson Yen, Ngok Ying Chu
  • Patent number: 9559727
    Abstract: Row decoding is performed on row codewords in an array in order to produce a row decoded array that includes row decoded column codewords. Column decoding is performed on the row decoded column codewords in order to produce a row and column decoded array that includes row and column decoded row codewords and row and column decoded column codewords. The number of row and column decoded row codewords that are not in a row codebook is determined and the number of row and column decoded column codewords that are not in a column codebook are determined. If the number not in the row codebook equals 0 and the number not in the column codebook equals 1, at least a data portion of the row and column decoded array is output.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 31, 2017
    Assignee: SK hynix memory solutions Inc.
    Inventors: Naveen Kumar, Zheng Wu, Jason Bellorado
  • Patent number: 9531354
    Abstract: A random number generator is disclosed. In some embodiments, the random number generator comprises two cross-coupled inverter chains, wherein each inverter chain comprises an odd number of gates including an input NAND gate; wherein when a clock signal input into the NAND gate of both inverter chains switches from low to high, the inverter chains start toggling until a noise induced phase difference automatically collapses the toggling after a random number of cycles; and wherein a random number generated by the random number generator is based on the random number of cycles.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: December 27, 2016
    Assignee: SK hynix memory solutions Inc.
    Inventor: Yukeun Sim
  • Patent number: 9529722
    Abstract: A locality associated with a read request is identified based at least in part on a read address included in the read request. A predicted read address is generated based at least in part on the locality. It is decided whether to permit the predicted read address to be prefetched; in the event it is decided to permit the predicted read address to be prefetched, data from the predicted read address is prefetched and the prefetched data is stored in a prefetch cache.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 27, 2016
    Assignee: SK hynix memory solutions Inc.
    Inventors: Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Zheng Wu, Arunkumar Subramanian
  • Patent number: 9529744
    Abstract: A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 27, 2016
    Assignee: SK hynix memory solutions Inc.
    Inventors: Kwok W. Yeung, Meng-Kun Lee, Gubo Huang
  • Patent number: 9507705
    Abstract: A method of managing a non-volatile memory system is described where data elements stored in a buffer are characterized by attributes and a write data tag is created for the data elements. A plurality of write data tag queues is maintained so that different data attributes may be applied as sorting criteria when the data elements are formed into pages for storage in the non-volatile memory. The memory system may be organized as a RAID system and a write data tag queue may be associated with a specific RAID group such that the data pages may be written from a buffer to the non-volatile memory in accordance with the results of sorting each write data queue. The data elements stored in the buffer may be received from a user, or be read from the non-volatile memory during the performance of system overhead operations.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 29, 2016
    Assignee: SK hynix memory solutions Inc.
    Inventor: David J. Pignatelli
  • Patent number: 9502127
    Abstract: Methods of determining distributions may include performing a number of hard reads, performing a number of background reads at a frequency based on the number of hard reads, and estimating a conditional probability density of a cell voltage based on the hard reads and the background reads.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: November 22, 2016
    Assignee: SK hynix memory solutions Inc.
    Inventors: Fan Zhang, David J. Pignatelli, June Lee
  • Patent number: 9419748
    Abstract: A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: August 16, 2016
    Assignee: SK Hynix memory solutions Inc.
    Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
  • Patent number: 9378097
    Abstract: Information associated with a neighborhood is obtained based at least in part on a source location. It is determined, based at least in part on the information associated with the determined neighborhood, whether to perform a copy back operation using a specified set of one or more read thresholds. In the event it is determined to perform the copy back operation using the specified set of read thresholds, the copy back operation is performed on the source location using the specified set of read thresholds.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: June 28, 2016
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Jason Bellorado, Marcus Marrow
  • Patent number: 9368233
    Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Patent number: 9348758
    Abstract: A method of relating the user logical block address (LBA) of a page of user data to the physical block address (PBA) where the data is stored in a RAID architecture reduces to size of the tables by constraining the location to which data of a plurality of LBAs may be written. Chunks of data from a plurality of LBAs may be stored in a common page of memory and the common memory pages is described by a virtual block address (VBA) referencing the PBA, and each of the LBAs uses the same VBA to read the data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 24, 2016
    Assignee: SK Hynix memory solutions inc.
    Inventor: David J. Pignatelli
  • Patent number: 9336885
    Abstract: A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Arunkumar Subramanian, Frederick K. H. Lee, Xiangyu Tang, Lingqi Zeng, Jason Bellorado
  • Patent number: 9305658
    Abstract: A read is performed using a first iteration of a read threshold voltage that is set to a default voltage to obtain a first characteristic. A second iteration of the read threshold voltage is generated using the default voltage and an offset. A read is performed using the second iteration of the read threshold voltage to obtain a second characteristic. A third iteration of the read threshold voltage is generated using the first and second characteristics. A read is performed using the third iteration of the read threshold voltage to obtain a third characteristic. It is determined if the third characteristic is one of the two characteristics closest to a stored characteristic. If so, a fourth iteration of the read threshold voltage is generated using the two closest characteristics.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: April 5, 2016
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Lingqi Zeng, Jason Bellorado, Frederick K. H. Lee, Arunkumar Subramanian
  • Patent number: 9300329
    Abstract: Decoding associated with a second error correction code and a first error correction code is performed. Ns first and second-corrected segments of data, first sets of parity information, and second sets of parity information are intersegment interleaved to obtain intersegment interleaved data, where the Ns segments of data, the Ns first sets of parity information, and the Ns second sets of parity information have had decoding associated with the first and the second error correction code performed on them (Ns is the number of segments interleaved together). Decoding associated with a third error correction code is performed on the intersegment interleaved data and interleaved parity information to obtain at least third-corrected interleaved data. The third-corrected interleaved data is de-interleaved.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 29, 2016
    Assignee: SK hynix memory solutions inc.
    Inventors: Naveen Kumar, Zheng Wu, Jason Bellorado, Lingqi Zeng, Marcus Marrow
  • Patent number: 9292394
    Abstract: An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SK Hynix memory solutions inc.
    Inventors: Yingquan Wu, Marcus Marrow