Patents Assigned to SK hynix memory solutions inc.
  • Coding architecture for multi-level NAND flash memory with stuck cells
    Patent number: 9047213
    Abstract: Encoded least significant bit (LSB) values are generated for a cell based at least in part on a readback value for the cell. The encoded LSB values is decoded in order to obtain one or more decoded LSB values. Encoded most significant bit (MSB) values are generated for the cell based at least in part on (1) the readback value for the cell and (2) the decoded LSB values. The encoded MSB values are decoded in order to obtain one or more decoded MSB values, wherein the bit positions of the decoded LSB values do not overlap with the bit positions of the decoded MSB values.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 2, 2015
    Assignee: SK hynix memory solutions inc.
    Inventor: Marcus Marrow
  • Error data generation and application for disk drive applications
    Patent number: 9043688
    Abstract: Generating error data associated with decoding data is disclosed, including: processing an input sequence of samples associated with data stored on media using a detector and a decoder during a global iteration; and generating one or more error values based at least in part on one or more decision bits output by the detector or the decoder and the input sequence of samples.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 26, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Kai Keung Chan, Xin-Ning Song, Jason Bellorado, Kwok W. Yeung
  • Soft input, soft output mappers and demappers for block codes
    Patent number: 9026881
    Abstract: A codebook which includes a plurality of messages and a plurality of codewords, a specified codeword bit value, and a specified message bit value are obtained. The LLR for bit ci in a codeword is generated, including by: identifying, from the codebook, those codewords where bit ci has the specified codeword bit value; for a message which corresponds to one of the codewords where bit ci has the specified codeword bit value, identifying those bits which have the specified message bit value; and summing one or more LLR values which correspond to those bits, in the message which corresponds to one of the codewords where bit ci has the specified codeword bit value, which have the specified message bit value.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: May 5, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Zheng Wu, Marcus Marrow
  • Error recovery using erasures for NAND Flash
    Patent number: 9021340
    Abstract: Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. The selected bits in the codeword is/are replaced with an erasure to obtain a codeword with one or more erasures. Error correction decoding is performed on the codeword with one or more erasures.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: April 28, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Xiangyu Tang
  • Blind and decision directed multi-level channel estimation
    Patent number: 9015540
    Abstract: Data which is read back from a multi-level storage device is received. For each bin in a set of bins, a portion of reads which fall into that particular bin and which are to be maintained is received. The set of bins is adjusted so that the read-back data, after assignment using the adjusted set of bins, matches the received portions of reads which are to be maintained.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: April 21, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Marcus Marrow, Jason Bellorado, Rajiv Agarwal
  • Heat dissipation device
    Patent number: 9013874
    Abstract: A heat dissipation device for an electronic device includes a base, a plurality of fins and at least one heat pipe. The base has a front surface and a rear surface opposite to the front surface. A heat-generating component of the electronic device is disposed adjacent to the rear surface. The plurality of fins extend from the front surface of the base. The heat pipe is disposed on the front surface of the base and in a cutout portion of the plurality of fins. The heat dissipation device, which removes heat from the heat-generating component, has a low profile and improved heat dissipation capability.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 21, 2015
    Assignee: SK hynix memory solutions inc.
    Inventor: Givargis George Kaldani
  • Inter-track interference cancelation for shingled magnetic recording
    Patent number: 9013817
    Abstract: Inter-track interference cancelation is disclosed, including: receiving an input sequence of samples associated with a track on magnetic storage; using a processor to generate inter-track interference (ITI) data associated with a first side track including by performing a correlation between the input sequence of samples and a sequence of data associated with the first side track.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 21, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Jason Bellorado, Marcus Marrow
  • Flash multiple-pass write with accurate first-pass write
    Patent number: 8995199
    Abstract: An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: March 31, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Meng-Kun Lee, Yingquan Wu
  • Defect scan and manufacture test
    Patent number: 8996954
    Abstract: A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 31, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Multiple interleavers in a coding system
    Patent number: 8984364
    Abstract: Second interleaved data is de-interleaved using a second interleaving mapping to obtain encoded data. The second interleaved data includes a copy of constrained data in the same sequence and having the same values as the constrained data. Also, the portion of the second interleaved data that includes the copy of the constrained data satisfies a modulation constraint associated with limiting a number of consecutive events to a maximum number of consecutive events. The encoded data is decoded to obtain first interleaved data and the first interleaved data is de-interleaved using a first interleaving mapping to obtain the constrained data, a copy of which is included in the second interleaved data, where the constrained data satisfies the modulation constraint.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng
  • Generating soft read values which optimize dynamic range
    Patent number: 8943386
    Abstract: Bin identification information for a cell is generated. An estimation function is received where the estimation function trends toward a maximum soft read value at a first end and trends toward a minimum soft read value at a second end. A soft read value is determined for the cell based at least in part on the bin identification information and the estimation function.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: January 27, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Marcus Marrow
  • Peel decoding for concatenated codes
    Patent number: 8943390
    Abstract: A codeword that is associated with one uncorrected codeword in a set of first codewords is selected from a set of third codewords. Error correction decoding is performed on the selected codeword using a third, systematic error correction code.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: January 27, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Yu Kou, Lingqi Zeng
  • Finding optimal read thresholds and related voltages for solid state memory
    Patent number: 8937838
    Abstract: An expected value associated with stored values in solid state storage, as well as a set of three or more points are obtained where the three or more points include a voltage and a value associated with stored values. Two points having ratios closest to the expected value are selected from the set. A voltage is determined based at least in part on the selected two points and the expected value.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 20, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Lingqi Zeng, Jason Bellorado, Frederick K. H. Lee, Arunkumar Subramanian
  • Generation of constrained pseudo-random binary sequences (PRBS)
    Patent number: 8935309
    Abstract: A signal is generated by obtaining an unconstrained random bit sequence. The unconstrained random bit sequence is modified to satisfy a constraint and the modified random bit sequence is output.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 13, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Kai Keung Chan, Xin-Ning Song
  • Error recovery for flash memory
    Patent number: 8929138
    Abstract: An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: January 6, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Yingquan Wu, Marcus Marrow
  • Storage of read thresholds for NAND flash storage using linear approximation
    Patent number: 8923066
    Abstract: A first read threshold associated with a first page in a block and a second read threshold associated with a second page in the block are received, where the first page has a first page number and the second page has a second page number. A slope and a y intercept are determined based at least in part on the first read threshold, the second read threshold, the first page number, and the second page number. The slope and the y intercept are stored with a block identifier associated with the block.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Arunkumar Subramanian, Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Frederick K. H. Lee
  • Generating read thresholds using gradient descent and without side information
    Patent number: 8923062
    Abstract: A next read threshold is determined by determining a first number of solid state storage cells having a stored voltage which falls into a first voltage range and determining a second number of solid state storage cells having a stored voltage which falls into a second voltage range. A gradient is determine by taking a difference between the first number of solid state storage cells and the second number of solid state storage cells. The next read threshold is determined based at least in part on the gradient.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Arunkumar Subramanian, Lingqi Zeng, Xiangyu Tang, Ameen Aslam
  • Data independent error computation and usage with decision directed error computation
    Patent number: 8924833
    Abstract: An analog front end is adjusted by determining a signal quality based at least in part on digital sample(s). If the signal quality satisfies one or more criteria, a data independent gain gradient and a data independent offset gradient are selected to adjust the analog front end, where the two gradients are generated without taking into consideration an instantaneous value of an expected signal. If the signal quality does not satisfy the criteria, a decision directed gain gradient and a decision directed offset gradient are selected to adjust the analog front end, where the two gradients are generated based at least in part on decision(s).
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 30, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Zheng Wu, Jason Bellorado, Marcus Marrow
  • Implementation of LDPC selective decoding scheduling
    Patent number: 8918696
    Abstract: A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: December 23, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kin Man Ng, Kwok W. Yeung, Lingqi Zeng, Yu Kou, Aditi R. Ganesan
  • Error recovery by modifying soft information
    Patent number: 8918705
    Abstract: One or more locations in a plurality of data bit sequences that do not satisfy parity and are associated with data bit sequences that are unable to be successfully error correction decoded are determined. Soft information associated with the determined locations is modified and error correction decoding using the modified soft information is performed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 23, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Yingquan Wu