Patents Assigned to SK hynix memory solutions inc.
  • Patent number: 8443244
    Abstract: A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges. A set of amounts corresponding to the set of bins is received where each amount in the set indicates an amount of read values which fall into the corresponding bin. One or more of the bin ranges is adjusted, including by: in the event there is a first bin range that is less than the received read value, increasing at least the first bin range and in the event there is a second bin range that is greater than the received read value, decreasing at least the second bin range.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 14, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Marcus Marrow, Jason Bellorado, Rajiv Agarwal
  • Patent number: 8443257
    Abstract: Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: May 14, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
  • Patent number: 8433981
    Abstract: Data is stored from a host. A flash memory is divided into a plurality of memory groups, the memory groups each comprising a plurality of flash memory blocks. A first portion of one of the plurality of memory groups is allocated for storing parity data of an error-correcting code for the memory group. A second portion of the memory group is allocated for storing data from the host. A flash memory block in the memory group is erased prior to writing the data from the host, wherein the flash memory block contains valid data. The erased valid data is recovered using the error-correcting code.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 30, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Rajiv Agarwal, Marcus Marrow
  • Patent number: 8418020
    Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 9, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
  • Patent number: 8413009
    Abstract: Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: April 2, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Kwok W. Yeung, Kin Ming Chan, Meng-Kun Lee