Abstract: Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.
Type:
Grant
Filed:
May 23, 2011
Date of Patent:
October 29, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Kwok W. Yeung, Kai Keung Chan, Paul K. Lai
Abstract: In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the unpadded data over the decision and reliability information corresponding to the unpadded data during message passing. Zero padding is removed from the decoded data.
Type:
Grant
Filed:
February 25, 2011
Date of Patent:
October 29, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
Abstract: Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.
Abstract: A set of one or more receiver parameters is adjusted. It is determined whether to adjust the set of receiver parameters. In the event it is determined to adjust the set of receiver parameters, a new set of values is generated for the set of receiver parameters using a cost function (where the cost function does not assume a noise signal in a receive signal to have a particular statistical distribution) and the set of receiver parameters is changed to have the new set of values.
Abstract: Adjusting receiving parameters without known data is disclosed, including: receiving an indication of whether data associated with a sector is error correcting code (ECC) uncorrectable; in the event that the indication is that the data is uncorrectable, determining a plurality of statistical information outputs using a detector; and using at least a subset of the plurality of statistical information outputs to adjust a set of one or more receiver parameters.
Abstract: Writing servo wedge code to a disk is disclosed. A first selected burst demodulation window is determined. A final radial head position is computed based at least in part on the first selected burst demodulation window. Servo wedge code is written to a disk based at least in part on the final radial head position.
Abstract: A signal error is determined by obtaining a known property of an expected signal. A signal is received and a signal error is determined based at least in part on the received signal and the known property of the expected signal.
Type:
Grant
Filed:
January 24, 2011
Date of Patent:
September 10, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Zheng Wu, Jason Bellorado, Marcus Marrow
Abstract: An access instruction associated with accessing a target location in a disk is obtained. A number of units until the target location is accessed is calculated. It is determined whether there is time for the group of logic to transition from a lower power state to an operational state; the determination is based at least in part on the number of units between a current location of a read head associated with the hard disk system and the target location which is different from the current location of the read head and a warm up time associated with the group of logic. If it is determined there is time, the group of logic is put into the lower power state.
Abstract: In a high frequency mode a multiphase voltage-controlled oscillator (VCO) generates a first plurality of signals where each has the desired frequency and a different phase. A phase interpolator generates the signal at the desired frequency and the desired phase using a first plurality of signals. In a low frequency mode the VCO generates a second plurality of signals where each has a frequency which is a multiple of the desired frequency and a different phase. A multiphase frequency divider generates a third plurality of signals by dividing the frequency of the second plurality to the desired frequency while maintaining a phase relationship with the second plurality of signals. The phase interpolator generates the signal at the desired frequency and the desired phase using the third plurality.
Abstract: Writing servo wedge code to a disk is disclosed. A wedge-to-wedge time interval is determined. At least until it is determined that a lock criterion is met: For each wedge-to-wedge time interval, a wedge frequency error is computed based on an adjustable clock. The clock is adjusted based on one or more of the wedge frequency errors. It is determined whether a lock criterion is met based on one or more of the wedge frequency errors. After the lock criterion is met, servo wedge code is written to the disk.
Abstract: A system for error recovery for flash memory comprises a receiver and an interface. The receiver is configured to receive a portion of data. The receiver is further configured to identify a logical type of the portion of data. The receiver is further configured to adjust a threshold for error recovery of the portion of data based at least in part on the logical type. The receiver is further configured to read the portion of data using the adjusted threshold. The interface is coupled to the receiver.
Abstract: Encoding is performed by putting a low-density parity-check (LDPC) generator matrix into partial quasi-cyclic form comprising an identity matrix, a parity generator matrix, a zero matrix and a remainder matrix. The parity generator matrix is quasi-cyclic and the remainder matrix is not quasi-cyclic. An encoder is used to generate LDPC encoded data using the parity generator matrix and without using the remainder matrix.
Type:
Grant
Filed:
March 2, 2011
Date of Patent:
August 6, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
Abstract: A system for adapting coefficients of a soft output Viterbi algorithm (SOVA) is disclosed. The system includes a receiver configured to select an output of an SOVA detector at least in part based on a criterion. The receiver is configured to store the selected output of the SOVA detector. The receiver is further configured to store a signal that corresponds to the stored selected output of the SOVA detector, wherein the input to the SOVA detector is derived from the signal. The receiver is further configured to adapt a plurality of coefficients of the SOVA detector at least in part based on the stored selected output of the SOVA detector, the stored signal, and a corresponding data pattern. The system includes an interface coupled to the receiver and configured to receive samples.
Type:
Grant
Filed:
May 27, 2011
Date of Patent:
July 16, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Kai Keung Chan, Kin Man Ng, Xin-Ning Song, Jason Bellorado
Abstract: The present application refers to a method for determining an extrinsic information input to an ECC decoder of a turbo equalizer. In one embodiment, a first loop-back signal is represented with a first number of bits, wherein the first loop-back signal comprises a signal looped back from an output of an ECC decoder. An output of a signal detector is represented with a second number of bits. An extrinsic information input to the ECC decoder is determined based at least in part on the first loop-back signal, the represented output of the signal detector, and at least one comparison with at least one predetermined threshold.
Abstract: An iterative error correction coding (ECC) decoder is configured to operate in a first higher-power and higher-performance operating mode. At least some part of a system that includes the iterative ECC decoder is monitored. It is determining whether to switch the iterative ECC decoder from the first higher-power and higher-performance operating mode to a second lower-power and lower-performance operating mode based at least in part on the monitoring. The iterative ECC decoder is configured to operate in the second lower-power and lower-performance operating mode in the event it is determined to switch operating modes.
Abstract: A technique for writing data is disclosed. The technique includes estimating an amount of additional voltage on a victim cell of a solid-state storage device caused by writing to one or more other cells in the solid-state storage device, determining a modified write value for the victim cell based at least in part on a desired value for the victim cell and the estimated amount of additional voltage, and writing the modified write value to the victim cell.
Abstract: Flash memory is written to by determining a measure of health for each of a plurality of locations in flash memory. At least one of the plurality of locations in flash memory is selected based at least in part on the determined measures of health and the selected location(s) in flash memory is/are written to.
Abstract: Low-density parity-check (LDPC) encoding is performed by encoding input data using a first sub-matrix of a parity check matrix to obtain intermediate data. The parity check matrix includes the first sub-matrix and a second sub-matrix having a matrix inversion. The intermediate data is encoded using the matrix inversion of the second sub-matrix of the parity check matrix.
Type:
Grant
Filed:
December 16, 2010
Date of Patent:
May 21, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Lingqi Zeng, Abhiram Prabhakar, Kin Man Ng, Yu Kou
Abstract: Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.
Type:
Grant
Filed:
March 2, 2011
Date of Patent:
May 14, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Lingqi Zeng, Yu Kou, Kin Man Ng, Kwok W. Yeung
Abstract: A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges. A set of amounts corresponding to the set of bins is received where each amount in the set indicates an amount of read values which fall into the corresponding bin. One or more of the bin ranges is adjusted, including by: in the event there is a first bin range that is less than the received read value, increasing at least the first bin range and in the event there is a second bin range that is greater than the received read value, decreasing at least the second bin range.
Type:
Grant
Filed:
April 25, 2012
Date of Patent:
May 14, 2013
Assignee:
SK hynix memory solutions inc.
Inventors:
Marcus Marrow, Jason Bellorado, Rajiv Agarwal