Patents Assigned to SK hynix memory solutions inc.
  • Patent number: 8681550
    Abstract: A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s).
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 25, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Yingquan Wu, Marcus Marrow
  • Patent number: 8681563
    Abstract: An indication to store a data value in Flash memory is received. An accurate coarse write is performed, including by storing a first voltage level in the Flash memory and setting a configuration setting to a first setting. The first voltage level, when interpreted using the configuration setting at the first setting, corresponds to the data value. A fine write is performed, including by storing a second voltage level in the Flash memory and setting the configuration setting of the Flash memory to a second setting. The second voltage level, when interpreted using the configuration setting at the second setting, corresponds to the data value.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 25, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Meng-Kun Lee, Yingquan Wu
  • Patent number: 8677218
    Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: March 18, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Lingqi Zeng, Yu Kou
  • Patent number: 8671326
    Abstract: A method of encoding user data into a first set of codewords using a first code, generating a first set of parity information based at least in part on the first set of codewords and at least a second code, and writing at least parity information associated with the first set of parity information to shingled magnetic recording storage. A method of performing decoding on a first set of read-back signal data read back from shingled magnetic recording storage and associated with a first set of codewords, and if decoding of at least one read-back signal in the first set of read-back signal data fails, performing decoding on at least some of a second set of read-back signal data associated with a set of parity information.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 11, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Yu Kou, Lingqi Zeng
  • Patent number: 8671335
    Abstract: A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: March 11, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kwok W. Yeung, Shih-Ming Shih
  • Patent number: 8665543
    Abstract: Inter-track interference cancelation is disclosed, including: receiving an input sequence of samples associated with a track on magnetic storage; using a processor to generate inter-track interference (ITI) data associated with a first side track including by performing a correlation between the input sequence of samples and a sequence of data associated with the first side track.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: March 4, 2014
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Jason Bellorado, Marcus Marrow
  • Patent number: 8659847
    Abstract: User level data associated with a location adjacent to a desired location on a magnetic disk storage is received. Media level data associated with the adjacent location is generated based at least in part on the user level data associated with the adjacent location; a processor which is configured to generate the media level data associated with the adjacent location is a same processor which is configured to generate media level data based at least in part on user level data during a write process. The media level data associated with the adjacent location is used to remove inter-track interference (ITI) associated with the adjacent location from a signal read back from the desired location.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: February 25, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kwok W. Yeung, Kin Man Ng, Kin Ming Chan
  • Patent number: 8659450
    Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 25, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Zheng Wu, Jason Bellorado, Marcus Marrow
  • Patent number: 8659846
    Abstract: An initial phase offset between a center track and a side track is determined. An initial side track pulse shape is determined using the initial phase offset and side track interference. The initial side track pulse shape minimizes a contribution of the side track interference to a center track bit. The contribution of the side track interference is removed from the center track bit using the initial side track pulse shape and the side track interference.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 25, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Naveen Kumar, Jason Bellorado, Marcus Marrow, Kai Keung Chan
  • Patent number: 8650459
    Abstract: A log-likelihood ratio (LLR) for a bit bi in a message is determined by generating a first term, including by summing LLRs corresponding to bits in a first codeword having a specified value. The first codeword has a corresponding first message and bit bi of the first message corresponds to a 0. A second term is generated, including by summing LLRs corresponding to bits in a second codeword having the specified value. The second codeword has a corresponding second message and bit bi of the second message corresponds to a 1. The LLR for bit bi in the message is generated based at least in part on the first term and the second term.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: February 11, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Zheng Wu, Marcus Marrow
  • Patent number: 8650466
    Abstract: An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within the first test error pattern is flipped to obtain a second test error pattern, wherein i?j.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: February 11, 2014
    Assignee: SK hynix memory solutions inc.
    Inventor: Yingquan Wu
  • Patent number: 8650453
    Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 11, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kin Man Ng, Lingqi Zeng, Yu Kou, Kwok W. Yeung
  • Publication number: 20140040706
    Abstract: An analog front end is adjusted by determining a signal quality based at least in part on digital sample(s). If the signal quality satisfies one or more criteria, a data independent gain gradient and a data independent offset gradient are selected to adjust the analog front end, where the two gradients are generated without taking into consideration an instantaneous value of an expected signal. If the signal quality does not satisfy the criteria, a decision directed gain gradient and a decision directed offset gradient are selected to adjust the analog front end, where the two gradients are generated based at least in part on decision(s).
    Type: Application
    Filed: August 9, 2013
    Publication date: February 6, 2014
    Applicant: SK hynix memory solutions inc.
    Inventors: Zheng Wu, Jason Bellorado, Marcus Marrow
  • Patent number: 8631311
    Abstract: A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 14, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kai Keung Chan, Yu Kou, Xin-Ning Song, Wing Hui
  • Publication number: 20140013188
    Abstract: A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s).
    Type: Application
    Filed: July 2, 2013
    Publication date: January 9, 2014
    Applicant: SK hynix memory solutions inc.
    Inventors: Yingquan Wu, Marcus Marrow
  • Patent number: 8621293
    Abstract: A value read back from storage and a set of bins are received. Each bin in the set of bins has a bin range. A bin corresponding to the read-back value is selected from the set of bins. The bin range of the selected bin is adjusted, based at least in part on the read-back value, so that the read-back value is more centered within the selected bin after adjustment.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: December 31, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Marcus Marrow, Jason Bellorado, Rajiv Agarwal
  • Patent number: 8607132
    Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: December 10, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng
  • Patent number: 8599621
    Abstract: An instruction to perform an erase on a group of one or more memory cells is sent. An indication that the erasure of the group of memory cells is unsuccessful is received. In response to receiving the indication that the erasure of the group of memory cells is unsuccessful, the value of a voltage threshold, associated with the group of memory cells, is changed to a new voltage threshold and the new voltage threshold and identification information associated with the group of memory cells is stored.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 3, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Kwok W. Yeung, Meng-Kun Lee
  • Publication number: 20130318286
    Abstract: A number of pulses to modify information stored in a given location in a plurality of locations is obtained for each of the plurality of locations in flash memory. A location having the largest number of pulses is selecting from the plurality of locations. The selected location is written to.
    Type: Application
    Filed: April 24, 2013
    Publication date: November 28, 2013
    Applicant: SK hynix memory solutions inc.
    Inventors: Rajiv Agarwal, Marcus Marrow
  • Patent number: 8589760
    Abstract: A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 19, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Yu Kou, Lingqi Zeng