Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A semiconductor device includes a first source region and a drain region disposed on a substrate; a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region; a first select gate disposed on one sidewall of the first gate stack; a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region; a second spacer disposed on an upper sidewall of the first select gate; a first control gate silicide layer disposed on the first control gate; and a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.

Abstract: A method for manufacturing a semiconductor device includes providing a high-voltage isolation capacitor region on a substrate, forming a bottom electrode in the high-voltage isolation capacitor region, forming an inter-metal dielectric layer on the bottom electrode, forming a low bandgap dielectric layer on the inter-metal dielectric layer, forming a first hard mask layer on the low bandgap dielectric layer, patterning the first hard mask layer and the low bandgap dielectric layer to form a patterned first hard mask layer and a patterned low bandgap dielectric layer, depositing a thick metal film on the patterned first hard mask layer and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top electrode in the high-voltage isolation capacitor region, such that the top electrode overlaps the patterned first hard mask layer and the patterned low bandgap dielectric layer.

Abstract: A semiconductor device includes a source region and a drain region formed on a substrate; a gate structure formed between the source region and the drain region; a field insulating layer formed between the gate structure and the drain region; a first field plate structure formed on the field insulating layer, formed on a same plane and material as the gate structure; a source metal wiring connected to the source region, the first field plate structure, and the second field plate structure; a drain metal wiring connected to the drain region; and an interlayer insulating layer formed under the source metal wiring and the drain metal wiring; and a second field plate structure formed on the interlayer insulating layer, formed between the first field plate structure and the drain region, and formed of a material different from a material of the first field plate structure.

Abstract: A manufacturing method for a semiconductor device, includes: forming a first gate structure and a second gate structure on a substrate; forming a deep trench isolation (DTI) hard mask on the first and second gate structures; forming a deep trench isolation disposed between the first gate structure and the second gate structure; depositing a first undoped oxide layer in the deep trench isolation; performing a first etch-back process on the first undoped oxide layer to remove a portion of the undoped oxide layer; depositing a first deep trench isolation (DTI) gap-fill layer on a remaining portion of the undoped oxide layer, and performing a second etch-back process on the first DTI gap-fill layer; depositing a second DTI gap-fill layer to seal the deep trench isolation, and forming a planarized second DTI gap-fill layer by a planarization process; and depositing a second undoped layer on the planarized second DTI gap-fill layer.

Abstract: A semiconductor device includes a high voltage region formed on a semiconductor substrate; a junction isolation region surrounding the high voltage region; a Schottky diode configured to supply a forward current to the high voltage region; a silicon controlled rectifier (SCR) region formed between the Schottky diode and the high voltage region; a drain region, a gate region and a source region formed in the SCR region; a P-type isolation region formed between the Schottky diode and the source region; a first SCR including a first N+ region and a first P+ region in contact with each other and formed in the drain region; a second SCR comprising a second N+ region and a second P+ region in contact with each other and formed in the gate region; and a third SCR comprising a third N+ region and a third P+ region in contact with each other and formed in the P-type isolation region.

Abstract: A semiconductor device includes a high side region and a low side region formed on a semiconductor substrate; a level shifter formed between the high side region and the low side region and including a source region, a gate region and a drain region; a guard ring formed adjacent to the level shifter; a first silicon controlled rectifier (SCR) disposed in the guard ring and including a first P-type highly doped (P+) region and a first N-type highly doped (N+) region formed on the semiconductor substrate; a second SCR disposed in the source region and including a second P+ region and a second N+ region; a third SCR disposed in the gate region and including a third P+ region and a third N+ region; and a fourth SCR disposed in the drain region and including a fourth P+ region and a fourth N+ region.

Abstract: A semiconductor device for ESD protection includes semiconductor substrate, an element isolation layer, and a first well region of a second conductivity type, and second and third well regions of a first conductivity type. The first, second and third well regions are formed below the element isolation layer and are spatially separated from each other. Three doped regions are formed on the first well region and connected to a voltage node (VN) terminal. Two doped regions are formed on the second well region and connected to a ground (GND) terminal. Two doped regions are formed on the third well region and connected to a power supply (VCC) terminal, and the semiconductor device is configured to perform a unidirectional silicon controlled rectifier (SCR) function between the VN terminal and the VCC terminal, and a bidirectional SCR function between the VCC terminal and the GND terminal.

Abstract: A semiconductor device includes a PN diode; a drain region; a source region; a gate region formed between the drain region and the source region; a first p-type guard ring and a NP guard ring surrounding the PN diode. The NP guard ring includes a n-type guard ring and a second p-type guard ring; a drain Silicon Controlled Rectified (SCR) formed in the drain region and including a highly-doped n-type drain region (N+ drain region) and a highly-doped p-type drain region (P+ drain region), the drain SCR electrically connected to a high voltage; a first guard ring SCR formed in the first p-type guard ring and including a first highly doped n-type region (first N+ region) and a first highly doped p-type region (first P+ region); and a second guard ring SCR formed in the NP guard ring and including a second N+ region and a second P+ region.

Abstract: A non-volatile memory device based on a fuse type memory cell array includes an eFuse cell array including a plurality of unit cells in matrix form, each unit cell having a first switching element and an eFuse; an address decoder configured to activate, based on an address input from an external device, a word line used for program operation or read operation among a plurality of word lines; a current controller configured to supply a program current used for the program operation or a read current used for the read operation; a bit line sense amplifier configured to sense digital data output from the eFuse cell array and output the digital data; and a control logic configured to control the program operation or the read operation to be performed based on a control signal input from the external device.

Abstract: A method of manufacturing a semiconductor device with a deep trench capacitor includes forming first and second deep trenches in a substrate; forming a highly doped first polysilicon layer in the first and second deep trenches; forming a dielectric layer on the highly doped first polysilicon layer; forming a highly doped second polysilicon layer on the dielectric layer; performing a first etch process on the highly doped second polysilicon layer to form first and second upper electrodes in the first and second deep trenches; forming an insulating layer; performing a second etch process on the insulating layer to form first and second spacers; forming a silicide layer; forming an inter-metal insulating layer on the silicide layer; forming contact plugs on the silicide layer; and forming a metal layer connected to each of the contact plugs. The highly doped first polysilicon layer is a single continuous layer formed in the first deep trench and the second deep trench.

Abstract: A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.

Abstract: A semiconductor device includes: a logic region and a non-volatile memory (NVM) region; a logic gate insulating film disposed on a substrate in the logic region; at least one gate oxidation acceleration ion implantation layer disposed in the NVM region; at least one NVM gate insulating film disposed on the at least one gate oxidation acceleration ion implantation layer; a logic gate electrode disposed on the logic gate insulating film; and at least one NVM gate electrode disposed on the at least one NVM gate insulating film, wherein a thickness of the at least one NVM gate insulating film is equal or greater than a thickness of the logic gate insulating film.

Abstract: A manufacturing method of a non-volatile memory device, includes forming a floating gate on a substrate, depositing a first insulating layer on the floating gate, depositing a second insulating layer on the first insulating layer, depositing a third insulating layer on the second insulating layer, performing a first etch-back process on the third insulating layer to form a spacer-shaped third insulating layer on the second insulating layer, performing a second etch-back process on the second insulating layer to form a spacer-shaped second insulating layer on the first insulating layer, and performing a wet etching to remove the spacer-shaped third insulating layer to form a spacer-shaped first insulating layer and the spacer-shaped second insulating layer on the floating gate.

Abstract: A semiconductor device including a bootstrap diode is provided. The semiconductor device comprises a first deep well region and a second deep well region disposed in a substrate; a pinch-off region disposed between the first and second deep well regions and configured to have a depth smaller than depths of the first and second deep well regions from a top surface of a substrate; a first buried layer and a second buried layer respectively disposed in the first and second deep well regions; a P-type source region and a N-type drain region respectively disposed in the first and second deep well regions; and a N-type sink region surrounding the P-type source region, where the N-type sink region has a doping concentration higher than a doping concentration of the first deep well region.

Abstract: A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

Abstract: A semiconductor device includes a bottom metal line and a bottom electrode disposed on a substrate, a thick inter-metal dielectric layer disposed on the bottom metal line and the bottom electrode, a first via disposed on the bottom metal line disposed in the thick inter-metal dielectric layer, a second via disposed on the first via, a top metal line disposed on the second via and overlapping the bottom metal line, a low bandgap dielectric layer disposed on the thick inter-metal dielectric layer, a hard mask layer disposed on the low bandgap dielectric layer, a top electrode disposed on the hard mask layer and overlapping the bottom electrode, and a passivation layer disposed on the top metal line and the top electrode.

Abstract: A semiconductor device includes a first source region and a drain region disposed on a substrate; a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region; a first select gate disposed on one sidewall of the first gate stack; a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region; a second spacer disposed on an upper sidewall of the first select gate; a first control gate silicide layer disposed on the first control gate; and a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.

Abstract: A semiconductor device is provided. The semiconductor device includes a logic region and a capacitor region, wherein the capacitor region comprises a bottom electrode disposed on a substrate; a top electrode disposed on the bottom electrode; a first inter-metal dielectric film disposed between the substrate and the bottom electrode; a second inter-metal dielectric film and a third inter-metal dielectric film disposed between the top electrode and the bottom electrode; a passivation film disposed on the top electrode, wherein the top electrode is configured to have a rounded top corner, and the bottom electrode is configured to have a sharp top corner.

Abstract: A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.