Abstract: A semiconductor device includes a P-type body region and an N-type drift region disposed in a substrate; a gate electrode, disposed on the P-type body region and the N-type drift region, including a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region; a spacer disposed on a side of the gate electrode; a highly doped source region disposed in the P-type body region; and a highly doped drain region disposed in the N-type body region. The high concentration doping region overlaps the P-type body region, and the high resistance region overlaps the N-type drift region.

Abstract: A semiconductor device including: a semiconductor substrate including a buried layer; and a deep trench isolation a predetermined depth disposed starting from an upper surface of the semiconductor substrate, wherein the deep trench isolation includes: a first point disposed near the upper surface of the semiconductor substrate; a second point disposed near the buried layer; and a third point disposed near a bottom face of the deep trench isolation, and wherein the deep trench isolation has an inclination such that a width of the deep trench isolation increases from the second point to the third point, is disclosed.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes depositing a first interconnect metal layer on a substrate; depositing a first barrier metal layer on the first interconnect metal layer; depositing a first dielectric layer on the first barrier metal layer; depositing a second barrier metal layer on the first dielectric layer; etching the second barrier metal layer to form a MIM capacitor region and a thin film resistor region; forming a hard mask on the second barrier metal layer and the first dielectric layer; forming an isolated interconnect pattern between the MIM capacitor region and the thin film resistor region; depositing an inter-metal dielectric layer on the hard mask; forming Via holes in the MIM capacitor region and the thin film resistor region, and filling the Via holes with metal to form a Via contact layer.

Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

Abstract: A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

Abstract: An analog-to-digital converter (ADC) and an operation method thereof are provided. The ADC includes: a comparator which compares a signal input through a first input terminal and a signal input through a second input terminal, and outputs an output value according to the comparison result. A successive approximation register receives the output value of the comparator, sets digital signal values from a most significant bit to a least significant bit, and outputs the digital signal values. A digital-to-analog converter receives the digital signal values, and converts it into an analog signal based on a reference voltage Vref, and outputs it to the second input terminal. A noise component is added to the input signal and to the analog signal Vdac'.

Abstract: The analog-to-digital converter (ADC) includes a sample and hold circuit configured to sample an analog input voltage and hold the sampled voltage. The sample and hold circuit includes: an analog switch configured to generate a boosting voltage obtained by adding a constant voltage to the analog input voltage, and output an analog output voltage corresponding to the analog input voltage by using the boosting voltage; and a capacitor in which the analog output voltage is charged.

Abstract: A memory device includes an eFuse cell array in which unit cells of different types are alternately disposed, and each of the unit cells of different types includes a PN diode, a first NMOS transistor, and a fuse, wherein a first type unit cell and a second type unit cell are connected to each other through a common node, and the first type unit cell and the second type unit cell are disposed in a bilaterally symmetrical structure with respect to the common node.

Abstract: A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

Abstract: A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells; and a sense amplifier configured to read data from the plurality of memory cells and output the read data. The sense amplifier includes a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes depositing a first interconnect metal layer on a substrate; depositing a first barrier metal layer on the first interconnect metal layer; depositing a first dielectric layer on the first barrier metal layer; depositing a second barrier metal layer on the first dielectric layer; etching the second barrier metal layer to form a MIM capacitor region and a thin film resistor region; forming a hard mask on the second barrier metal layer and the first dielectric layer; forming an isolated interconnect pattern between the MIM capacitor region and the thin film resistor region; depositing an inter-metal dielectric layer on the hard mask; forming Via holes in the MIM capacitor region and the thin film resistor region, and filling the Via holes with metal to form a Via contact layer.

Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.

Abstract: An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.

Abstract: A first high voltage semiconductor element, disposed in a substrate, includes first trenches; a first source region and a first drain region; first drift regions having respective ones partially surround the first source region and the first drain region; a first gate insulating layer and a first gate electrode disposed between the first drift regions; and a first high voltage well surrounding the first drift regions. A second high voltage semiconductor element, disposed in the substrate, includes second trenches; a second source region and a second drain region; second drift regions having respective ones partially surround the second source region and the second drain region; a second gate insulating layer and a second gate electrode disposed between the second drift regions; and a second high voltage well surrounding the second drift regions. Depths of the second trenches are disposed to be greater than depths of the first trenches.

Abstract: A memory device includes an eFuse cell array in which unit cells of different types are alternately disposed, and each of the unit cells of different types includes a PN diode, a first NMOS transistor, and a fuse, wherein a first type unit cell and a second type unit cell are connected to each other through a common node, and the first type unit cell and the second type unit cell are disposed in a bilaterally symmetrical structure with respect to the common node.

Abstract: An analog-to-digital converter (ADC) and an operation method thereof are provided. The ADC includes: a comparator which compares a signal input through a first input terminal and a signal input through a second input terminal, and outputs an output value according to the comparison result. A successive approximation register receives the output value of the comparator, sets digital signal values from a most significant bit to a least significant bit, and outputs the digital signal values. A digital-to-analog converter receives the digital signal values, and converts it into an analog signal based on a reference voltage Vref, and outputs it to the second input terminal. A noise component is added to the input signal and to the analog signal Vdac?.

Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate

Abstract: A non-volatile memory device, includes a source region and a drain region disposed in a channel length direction on a substrate; a flash cell, including a floating gate and a control gate, disposed between the source region and the drain region; a selection gate disposed between the source region and the flash cell; a selection line connecting the selection gate; a word line connecting the control gate; a common source line connected to the source region; and a bit line connected to the drain region.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.