Abstract: A semiconductor device, includes an insulating film formed on a substrate; a conductive layer, comprising first and second doped poly-silicon regions and a undoped poly-Si region, formed on the insulating film; a highly doped first conductivity type drain region and a highly doped a first conductivity type source region formed in the first and second doped poly-silicon regions, respectively; and a highly doped second conductivity type gate region formed in the undoped poly-Si region between the highly doped first conductivity type drain region and the highly doped first conductivity type source region. The undoped poly-Si region is disposed closer to the highly doped first conductivity type source region than the highly doped first conductivity type drain region.

Abstract: A semiconductor device including a CMOS process-based Hall sensor is provided. The semiconductor device which may include a N-type sensing region which is formed on a semiconductor substrate; P-type contact regions and N-type contact regions which are alternately formed in the N-type sensing region; a plurality of first trenches which are formed in contact with the P-type contact regions and have a first width; and a plurality of second trenches which separate the P-type contact regions and the N-type contact regions and have a second width less than the first width.

Abstract: A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

Abstract: A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.

Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.