Patents Assigned to Soitec
  • Publication number: 20200013921
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Application
    Filed: February 26, 2018
    Publication date: January 9, 2020
    Applicant: Soitec
    Inventor: David Sotta
  • Patent number: 10510565
    Abstract: A thermal treatment system includes a chamber capable of receiving a plurality of substrates, a gas intake path in a distal portion of the chamber located opposite an area for entry of substrates into the chamber, and an outlet path for the gas and/or volatile species generated during the thermal treatment. The outlet path is located in a proximal portion of the chamber located near the area for entry of the substrates into the chamber. The system further includes a collector device in the proximal portion of the chamber. The collector device has a confinement opening oriented toward the distal portion of the chamber, and the collector device defines a compartment communicating with the outlet path, the compartment being configured so that the gas and the volatile species enter into the compartment via the confinement opening and pass through the compartment to reach the outlet path.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: December 17, 2019
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Sébastien Simon
  • Patent number: 10510531
    Abstract: A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 17, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Isabelle Bertrand, Luciana Capello, Marcel Broekaart
  • Patent number: 10509214
    Abstract: A method for determining the size of a void-type defect in a top side of a structure comprising a top layer placed on a substrate, the defect being located in the top layer, includes introducing the structure into a reflected darkfield microscopy device in order to generate, from a light ray scattered by the top side, a defect-related first signal and a roughness-related second signal. The intensity of the roughness-related second signal is captured with a plurality of pixels. The intensity captured by each pixel is compared with the intensities captured by neighboring pixels. It is defined whether or not the pixel is contained in an abnormal zone. The standard deviation of the intensity values captured by the pixels of the abnormal zone is extracted, and the size of the void-type defect associated with the abnormal zone is determined from the extracted standard deviation. A new device may be used for carrying out such a method.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 17, 2019
    Assignee: Soitec
    Inventor: Olivier Pfersdorff
  • Patent number: 10490688
    Abstract: A semiconductor device, in particular a solar cell is formed on the basis of a hybrid deposition strategy using MOCVD and MBE in order to provide lattice matched semiconductor compounds. To this end, the MBE may be applied for providing a nitrogen-containing semiconductor compound that allows a desired low band gap energy and a lattice matched configuration with respect to gallium arsenide substrates.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: November 26, 2019
    Assignee: Soitec
    Inventors: Rainer Krause, Bruno Ghyselen
  • Patent number: 10453739
    Abstract: A method of transferring blocks of semiconductor material to a substrate comprises the following steps: a. providing an intermediate substrate, the intermediate substrate comprising, on one of its faces, blocks, the blocks comprise a monocrystalline material, the blocks comprising an embrittlement area delimiting a block portion intended to be transferred onto a final substrate; b. executing an assembling step by putting a free surface of each of the blocks in contact with the final substrate; and c. executing, after the assembling step, detachment at the embrittlement area of each of the blocks. During the assembling step, the intermediate substrate deforms so that the free surfaces of the blocks become coplanar.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: October 22, 2019
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 10429436
    Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: October 1, 2019
    Assignee: Soitec
    Inventors: Cédric Malaquin, Jean-Pierre Raskin, Eric Desbonnets
  • Patent number: 10361326
    Abstract: This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 23, 2019
    Assignee: Soitec
    Inventors: Cécile Aulnette, Rainer Krause, Frank Dimroth, Eric Guiot, Eric Mazaleyrat, Charlotte Drazek
  • Publication number: 20190221471
    Abstract: A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.
    Type: Application
    Filed: August 1, 2017
    Publication date: July 18, 2019
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, Soitec, Soitec
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frederic Mazen, Damien Massy, Shay Reboh, Francois Rieutord
  • Patent number: 10347597
    Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: July 9, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, William Van Den Daele, Eric Desbonnets
  • Patent number: 10343902
    Abstract: A method for manufacturing a structure comprises a) providing a donor substrate comprising front and rear faces; b) providing a support substrate; c) forming an intermediate layer on the front face of the donor substrate or on the support substrate; d) assembling the donor and support substrates with the intermediate layer therebetween; e) thinning the rear face of the donor substrate to form a useful layer of a useful thickness having a first face disposed on the intermediate layer and a second free face; and wherein the donor substrate comprises a buried stop layer and a fine active layer having a first thickness less than the useful thickness, between the front face of the donor substrate and the stop layer; and after step e), removing, in first regions of the structure, a thick active layer delimited by the second free face of the useful layer and the stop layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 9, 2019
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Publication number: 20190181035
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.
    Type: Application
    Filed: May 17, 2017
    Publication date: June 13, 2019
    Applicant: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Publication number: 20190157137
    Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms·cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms·cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.
    Type: Application
    Filed: June 6, 2017
    Publication date: May 23, 2019
    Applicant: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 10297464
    Abstract: A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 21, 2019
    Assignee: Soitec
    Inventors: Marcel Broekaart, Luciana Capello, Isabelle Bertrand, Norbert Colombet
  • Patent number: 10283364
    Abstract: The invention concerns an assembly method comprising the following steps: a) providing a first substrate comprising a first face made from crystalline indium phosphide, b) providing a second substrate comprising a second crystalline face different from the indium phosphide, c) forming an intermediate layer of crystalline indium phosphide on the second face of the second substrate, d) forming an assembly, via a direct bonding step, by bringing the first face of the first substrate into contact with the intermediate layer, the direct bonding step being carried out in an atmosphere having a pressure greater than 10?4 Pa, and preferably higher than 10?3 Pa, e) subjecting the assembly formed in step d) to heat treatment.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 7, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Bruno Imbert, Hubert Moriceau, Xavier Blot
  • Patent number: 10276492
    Abstract: Methods of forming a semiconductor structure include forming a device layer on an initial substrate, attaching a first surface of the device layer to a temporary substrate and forming a high resistivity layer on a second surface of the device layer by removing a portion of the initial substrate. Methods further include attaching a final substrate to the high resistivity layer and removing the temporary substrate. Semiconductor structures are fabricated by such methods that include a final substrate, a high resistivity layer disposed over the final substrate and a device layer disposed over the high resistivity layer.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Soitec
    Inventors: Ionut Radu, Eric Desbonnets
  • Patent number: 10270413
    Abstract: This disclosure relates to a method of fabrication of a surface acoustic wave device comprising the step (a) of providing a piezoelectric structure, the step (b) of providing a dielectric structure, wherein the step (b) comprises a step (b1) of metalizing the dielectric structure, and the method further comprising the step (c) of bonding the metalized dielectric structure to the piezoelectric structure.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 23, 2019
    Assignee: Soitec
    Inventors: Christophe Zinke, Eric Desbonnets
  • Patent number: 10250282
    Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower than 10,000 ohm·cm over a temperature range extending from ?20° C. to 120° C.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 2, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Didier Landru, Christophe Figuet
  • Publication number: 20190088462
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Application
    Filed: July 13, 2016
    Publication date: March 21, 2019
    Applicants: Soitec, Soitec
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Patent number: 10220603
    Abstract: The disclosure relates to a method for separating a layer from a composite structure, the structure comprising a composite stack formed from at least a support substrate, which is partially transparent at a determined wavelength, the layer to be separated and a separation layer interposed between the support substrate and the layer to be separated, the method comprising irradiation of the separation layer through the support substrate by means of incident light ray at the determined wavelength in order to induce weakening or separation by exfoliation of the separation layer, the light ray being inclined so as to form an angle of incidence ? such that ?>?min, where ?min=sin?1((n1/n0)sin(tan?1(s/2h))), n1 and n0, respectively, being the refractive index of the support substrate and the refractive index of the external medium in contact with the support substrate, from which the ray comes, S being the width of the ray and h being the thickness of the support substrate.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 5, 2019
    Assignee: Soitec
    Inventor: Didier Landru