Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

Abstract: A method of manufacturing a composite structure comprises: a) providing a donor substrate of a single-crystal semiconductor material, b) implanting ions into the donor substrate, excluding an annular peripheral region, to form a buried brittle plane, the implantation conditions defining a first thermal budget for obtaining bubbling on a face of the donor substrate and a second thermal budget for obtaining a fracture in the brittle plane, c) forming a stiffening film on the donor substrate, carried out by applying a thermal budget lower than the first thermal budget, the stiffening film being perforated in the form of a mesh, the perforated stiffening film leaving a plurality of zones of the front face bare, d) depositing a carrier substrate on the donor substrate carried out by applying a thermal budget greater than the first thermal budget, and e) separating the donor substrate along the brittle plane.

Abstract: A method for producing a multilayer structure includes the following steps: a) providing a first substrate, b) depositing a thick layer of a precursor formulation including a preceramic polymer filled with inorganic particles on the first substrate, c) providing a second substrate, d) adhesively bonding the thick layer and the second substrate, e) thinning the first substrate or the second substrate so as to obtain an active layer, f) applying a pyrolysis heat treatment so as to ceramize the preceramic polymer of the thick layer and to obtain a ceramic matrix composite material, the filler content and the nature of the inorganic particles being chosen so that the thick layer has a coefficient of thermal expansion which differs, at most, by 15% from that of the first substrate and from that of the second substrate.

Abstract: A temporary substrate, which is detachable at a detachment temperature higher than 1000° C. comprises: a semiconductor working layer extending along a main plane, a carrier substrate, an intermediate layer having a thickness less than 20 nm arranged between the working layer and the carrier substrate, a bonding interface located in or adjacent the intermediate layer, gaseous atomic species distributed according to a concentration profile along the axis normal to the main plane, the atoms remaining trapped in the intermediate layer and/or in an adjacent layer of the carrier substrate with a thickness less than or equal to 10 nm and/or in an adjacent sublayer of the working layer with a thickness less than or equal to 10 nm when the temporary substrate is subjected to a temperature lower than the detachment temperature.

Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

Abstract: A transducer structure for a surface acoustic device comprises a composite substrate comprising a piezoelectric layer, a pair of inter-digitated comb electrodes, comprising a plurality of electrode means with a pitch p satisfying the Bragg condition, wherein the inter-digitated comb electrodes are embedded in the piezoelectric layer such that, in use, the excitation of a wave propagating mode in the volume of the electrode means is taking place and is the predominant propagating mode of the structure. The present disclosure relates also to an acoustic wave device comprising at least one transducer structure as described above and to a method for fabricating the transducer structure. The present disclosure relates also to the use of the frequency of the bulk wave propagating in the electrode means of the transducer structure in an acoustic wave device to generate contribution at high frequency, in particular, above 3 GHz.

Abstract: A composite structure for an acoustic wave device comprising a heterostructure includes: a useful layer of piezoelectric material, having a first face and a second face, the first face being arranged at a first bonding interface on a support substrate having a coefficient of thermal expansion less than that of the useful layer, wherein the composite structure further comprises a functional layer, an entire surface of which is arranged at a second bonding interface on the second face of the useful layer and having a coefficient of thermal expansion less than that of the useful layer. Methods are used for producing such a composite structure.

Abstract: A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: —regions of direct contact between the working layer and the carrier substrate; and —agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.

Abstract: An acoustic wave sensor device comprises a first interdigitated transducer, a first reflection structure, a second reflection structure, a first resonance cavity comprising a first upper surface and formed between the first interdigitated transducer and the first reflection structure, and a second resonance cavity comprising a second upper surface and formed between the first interdigitated transducer and the second reflection structure. At least one of the first and second upper surfaces is covered at least partly by a metalization layer or a passivation layer. The present invention relates also to an acoustic wave sensor assembly.

Abstract: A resonator device for measuring stress comprises at least two resonators, each resonator comprising an inter-digitated transducer structure arranged between two reflecting structures on or in a piezoelectric substrate, wherein the at least two resonators are arranged and positioned such that they have two different wave propagation directions, and each resonator comprises at least two parts with the area between the two parts of the at least two resonators forming a cavity, wherein the cavity is shared by the at least two resonators and wherein for at least one resonator, in particular, all resonators, the inter-digitated transducer structure comprises a first material and the reflecting structures a second material different from the first material and/or the inter-digitated transducer structure and the reflecting structures have different geometrical parameters. A differential sensing device comprises at least one resonator device as described herein.

Abstract: An NCFET transistor comprises a semiconductor-on-insulator substrate for a field-effect transistor, and the NCFET transistor successively comprises, from its base to its surface: a semiconductor carrier substrate; a single ferroelectric layer, arranged in direct contact with the carrier substrate, which layer is designed to be biased so as to form a negative capacitance; and an active layer of a semiconductor material, which layer is designed to form the channel of the transistor, and is arranged in direct contact with the ferroelectric layer. The NCFET transistor further comprises a channel that is arranged in the active layer, a source and a drain that are arranged in the active layer on either side of the channel, and a gate that is arranged on the channel and is insulated from the channel by a gate dielectric.

Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a first free surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer, wherein the useful layer comprises an area of nanocavities.

Abstract: A method for forming a high resistivity handle substrate for a composite substrate comprises: providing a base substrate made of silicon; exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer having a thickness of at least 10 nm on the surface of the base substrate; and then growing a polycrystalline charge trapping layer on the carbon-containing layer.

Abstract: A holding device for a fracturable assembly, which is intended to separate along a fracture plane defined between an upper part and a lower part of the fracturable assembly, comprises at least two protrusions configured to keep the fracturable assembly suspended in a substantially horizontal holding position, the protrusions being intended to be located between the upper part and the lower part, against a peripheral chamfer of the upper part; a support located below and at a distance from the protrusions so as to gravitationally receive the lower part when the fracturable assembly is separated, and to keep it at a distance from the upper part held by the protrusions.

Abstract: A detachment chamber for detaching a piezoelectric layer from a piezoelectric donor substrate includes at least one chuck having at least one electrode configured to apply an electric field to the piezoelectric donor substrate to detach the piezoelectric layer from the piezoelectric donor substrate.

Abstract: A support substrate for a radiofrequency application comprises: —a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm·cm and strictly less than 500 ohm·cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, —an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm·cm, —a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm·cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.

Abstract: A transducer structure with means for transverse mode suppression comprises a piezoelectric substrate, and a pair of inter-digitated comb electrodes on the piezoelectric substrate. The first comb electrode has a first bus bar and a plurality of electrode fingers alternating with shorter dummy fingers, both extending from the first bus bar. The second comb electrode has a second bus bar and a plurality of electrode fingers extending from the second bus bar. The dummy fingers of the first bus bar face the fingers of the second bus bar and are separated from the fingers by first gaps. A transverse mode suppression layer is disposed partially underneath the first gap. The phase velocity of a guided wave is smaller in the region of the transverse mode suppression layer compared to the phase velocity of the guided wave in the central region underneath the alternating fingers of the first and second electrodes.

Abstract: A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

Abstract: A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

Abstract: A hybrid structure includes a support substrate having a first coefficient of thermal expansion and a support thickness, and an effective layer disposed on and molecularly bonded to the support substrate along a bonding interface having a bonding energy greater than or equal to 1000 mJ/m2. The effective layer has an effective thickness and a second coefficient of thermal expansion greater than the first coefficient of thermal expansion of the support substrate. One or more non-bonded areas are present at the bonding interface between the effective layer and the support substrate. The effective thickness is less than a threshold thickness at which buckling of the effective layer occurs upon annealing of the hybrid structure at a temperature of 400° C.±200° C.