Patents Assigned to Soitec
  • Publication number: 20250137928
    Abstract: A method and device for monitoring the weakening of an interface between a layer and a substrate while a weakening anneal is being carried out. The method includes illuminating the first face of the substrate layer assembly with a monochromatic light beam in a first direction; measuring the intensity of the light beam scattered by the substrate layer assembly in at least a second direction, the second direction forming a non-zero angle with the first direction; and determining a state of weakening of the interface from the intensity.
    Type: Application
    Filed: February 14, 2023
    Publication date: May 1, 2025
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Frédéric MAZEN, François RIEUTORD, Samuel TARDIF, Didier LANDRU, Oleg KONONCHUK, Nadia BEN MOHAMED
  • Patent number: 12289100
    Abstract: A coupled cavity filter structure that uses a surface acoustic wave, in particular, a guided surface acoustic wave, comprises an acoustic wave propagating substrate, at least one input transducer structure and one output transducer structure, provided over the substrate, each comprising inter-digitated comb electrodes, at least one reflecting structure comprising at least one or more metallic strips positioned at a distance and in between the input and output transducer structures, in the direction of propagation of an acoustic wave. The acoustic wave propagating substrate is a composite substrate comprising a base substrate and a piezoelectric layer. In additional embodiments, a coupled cavity filter structure comprises a groove. In additional embodiments, a SAW ladder filter device comprises at least two coupled cavity filter structures as described herein, wherein the at least two coupled cavity filter structures are positioned on a single line.
    Type: Grant
    Filed: June 26, 2024
    Date of Patent: April 29, 2025
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Thierry LaRoche
  • Patent number: 12278608
    Abstract: A process for fabricating a substrate for a radiofrequency device includes providing a piezoelectric substrate and a carrier substrate, depositing a dielectric layer on a surface of the piezoelectric substrate, assembling together the piezoelectric substrate and the carrier substrate with a polymerizable adhesive directly between the dielectric layer and the carrier substrate to form an assembled substrate, and polymerizing the polymerizable adhesive layer to form a polymerized layer bonding the piezoelectric substrate to the carrier substrate, the polymerized layer and the dielectric layer together forming an electrically insulating layer between the piezoelectric substrate and the carrier substrate.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: April 15, 2025
    Assignee: SOITEC
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 12272540
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: April 8, 2025
    Assignee: SOITEC
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Patent number: 12272720
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: April 8, 2025
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 12270123
    Abstract: A method for producing a substrate for the epitaxial growth of a gallium-based III-N alloy layer comprises the following successive steps: —providing a donor substrate of single-crystal silicon carbide; —implanting ions in the donor substrate to form an embrittlement zone defining a thin film layer of single-crystal SiC; —bonding the donor substrate onto a first receiving substrate via a bonding layer; —detaching the donor substrate along the embrittlement zone to transfer the thin film of SiC onto the first receiving substrate; —epitaxially growing a layer of semi-insulating SiC having a thickness greater than 1 ?m on the thin film of SiC; —bonding the layer of semi-insulating SiC onto a second receiving substrate having a high electrical resistivity; —removing at least a portion of the bonding layer to detach the first receiving substrate; and —removing the transferred thin film of single-crystal SiC, to expose the semi-insulating SiC layer.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: April 8, 2025
    Assignee: Soitec
    Inventor: Eric Guiot
  • Patent number: 12271774
    Abstract: A surface acoustic wave tag device is disclosed, comprising: an acoustic wave propagating substrate, at least one transducer structure comprising inter-digitated comb electrodes, and at least one reflecting means, the reflecting means comprising at least one reflector, wherein the acoustic wave propagation substrate is a composite substrate comprising a base substrate and a piezoelectric layer, wherein the crystallographic orientation of the piezoelectric layer with respect to the base substrate is such that the propagation of a shear wave inside the piezoelectric layer and in the direction of propagation corresponding to the acoustic wave is enabled. A physical quantity determining device and a fabrication method of such surface acoustic wave tag device are also disclosed.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 8, 2025
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Thierry LaRoche
  • Patent number: 12261079
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: March 25, 2025
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 12255634
    Abstract: A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: March 18, 2025
    Assignee: SOITEC
    Inventors: Eric Michoulier, Sylvain Ballandras, Thierry LaRoche
  • Patent number: 12255612
    Abstract: A surface acoustic wave device comprising a base substrate, a piezoelectric layer and an electrode layer in between the piezoelectric layer and the base substrate, a comb electrode formed on the piezoelectric layer comprising a plurality of electrode means with a pitch p, defined asp=A, with A being the wavelength of the standing acoustic wave generated by applying opposite potentials to the electrode layer and comb electrode, wherein the piezoelectric layer comprises at least one region located in between the electrode means, in which at least one physical parameter is different compared to the region underneath the electrode means or fingers. A method of fabrication for such surface acoustic wave device is also disclosed. The physical parameter may be thickness, elasticity, doping concentration of Ti or number of protons obtained by proton exchange.
    Type: Grant
    Filed: February 21, 2024
    Date of Patent: March 18, 2025
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Thierry LaRoche
  • Patent number: 12234144
    Abstract: A method for sealing cavities using membranes, the method including a) forming cavities arranged in a matrix, of a depth p, a characteristic dimension a, and spaced apart by a spacing b; and b) forming membranes, sealing the cavities, by transferring a sealing film. The method further includes a step a1), executed before step b), of forming a first contour on the front face and/or on the sealing face, the first contour comprising a first trench having a width L and a first depth p1, the formation of the first contour being executed such that after step b) the cavities are circumscribed by the first contour, said first contour being at a distance G from the cavities between one-fifth of b and five b.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 25, 2025
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thierry Salvetat, Bruno Ghyselen, Lamine Benaissa, Caroline Coutier, Gweltaz Gaudin
  • Patent number: 12230533
    Abstract: A method for fabricating a semiconductor-on-insulator structure involves providing a donor substrate comprising a weakened zone delimiting a layer to be transferred, providing a receiver substrate, and bonding the donor substrate to the receiver substrate. The layer to be transferred is located on the bonding-interface side. A bonding wave is initiated at a first region on the periphery of the interface, and the wave is propagated toward a second region on the periphery of the interface opposite the first region. The difference in speed of propagation of the bonding wave between a central portion of the interface and a peripheral portion of the interface is controlled such that the speed of propagation of the bonding wave is lower in the central portion than in the peripheral portion. The donor substrate is detached along the weakened zone to transfer the layer to be transferred to the receiver substrate.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 18, 2025
    Assignee: Soitec
    Inventors: Marcel Broekaart, Arnaud Castex
  • Publication number: 20250054762
    Abstract: A method for manufacturing disassemblable substrates, comprising: (a) providing a first substrate comprising implanted species forming a flat implantation zone and a proximal surface; a second substrate comprising a surface; (b) forming a series of cavities on the proximal surface of the first substrate and/or on the surface of the second substrate; (c) assembling the first and second substrates (1, 2) by direct bonding; and (d) applying a heat treatment to weaken the flat implantation zone. Further, the series of cavities being arranged in such a way as to allow direct bonding between the first and second substrates during step (c); and prevent thermal initiation of the splitting of the weakened flat implantation zone at the end of step (d).
    Type: Application
    Filed: December 19, 2022
    Publication date: February 13, 2025
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thierry SALVETAT, Guillaume BERRE, François- Xavier DARRAS
  • Patent number: 12218201
    Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about ?0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 4, 2025
    Assignees: National University of Singapore, Soitec
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Walter Schwarzenbach, Gong Xiao, Aaron Thean, Chen Sun, Haiwen Xu
  • Patent number: 12198983
    Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 14, 2025
    Assignee: Soitec
    Inventors: Ionut Radu, Hugo Biard, Christophe Maleville, Eric Guiot, Didier Landru
  • Patent number: 12198975
    Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: January 14, 2025
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot
  • Patent number: 12183624
    Abstract: A process for producing a receiver substrate for a semiconductor-on-insulator structure for radiofrequency application comprises the following steps:—providing a semiconductor substrate comprising a base substrate made of monocrystalline material and a charge-trapping layer made of polycrystalline silicon arranged on the base substrate;—oxidizing the charge-trapping layer to form an oxide layer arranged on the charge-trapping layer. The oxidation of the charge-trapping layer is performed at least partly at a temperature lower than or equal to 875° C., in the following manner:—starting the oxidization at a first temperature (T1) between 750° C. and 1000° C.;—decreasing the temperature down to a second temperature (T2), lower than the first temperature (T1), between 750° C. and 875° C.;—continuing the oxidization at the second temperature (T2).
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: December 31, 2024
    Assignee: Soitec
    Inventors: Marcel Broekaart, Damien Parissi
  • Patent number: 12176244
    Abstract: A method for bonding a first substrate and a second substrate comprises bringing the first and second substrates into contact and implementing heating of a peripheral zone of at least one of the first and second substrates. The heating is initiated before the substrates are brought into contact and continued at least until the substrates are brought into contact in the zone. The heating is implemented by an infrared lamp configured to emit radiation having an outer boundary corresponding to the edge of the substrates.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 24, 2024
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Laurent Viravaux
  • Patent number: 12178133
    Abstract: A design process is used for designing a device comprising a plurality of micro-machined elements, each comprising a flexible membrane, the elements being arranged in a plane in a determined topology. The design process comprises a step of defining the determined topology so that it has a character compatible with a generic substrate having cavities, the characteristics of which are pre-established. Each flexible membrane of the micro-machined elements is associated with one cavity of the generic substrate. The present disclosure also relates to a fabrication process for fabricating a device comprising a plurality of micro-machined elements, and to this device itself, wherein only some of the pairs of cavities and flexible membranes are configured to form a set of functional micro-machined elements.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: December 24, 2024
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 12165900
    Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: December 10, 2024
    Assignee: Soitec
    Inventors: Marcel Broekaart, Ionut Radu, Didier Landru