Patents Assigned to Soitec
  • Patent number: 11901483
    Abstract: An optoelectronic semiconductor structure (SC) comprises an active InGaN-based layer disposed between an n-type injection layer and a p-type injection layer, the active p-type injection layer comprising a first InGaN layer and, disposed on the first layer, a second layer composed of a plurality of AlGaInN elemental layers, each elemental layer having a thickness less than its critical relaxation thickness, two successive elemental layers having different aluminum and/or indium and/or gallium compositions.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 13, 2024
    Assignee: Soitec
    Inventor: Mariia Rozhavskaia
  • Patent number: 11894830
    Abstract: A surface acoustic wave device includes at least one transducer; two acoustic reflectors disposed on either side of the at least one transducer so as to form a cavity, each acoustic reflector comprising an array of electrodes in the form of lines parallel with each other, each array comprising a subset of electrodes connected to a reference potential denoted mass defining a first connection type, and a subset of electrodes that are not connected to any potential, i.e. that have a floating connection defining a second connection type; at least one switching circuit configured to modify the distribution of the connections of at least one part of the electrodes of each array between the different connection types.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: February 6, 2024
    Assignees: THALES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, SOITEC SA, YNCREA HAUTS DE FRANCE ISEN LILLE, UNIVERSITE DE LILLE, ECOLE CENTRALE DE LILLE, UNIVERSITE POLYTECHNIQUE HAUTS-DE-FRANCE
    Inventors: Thi Mai Pham Colomban, Claude Prévot, Paolo Martins, Anne-Christine Hladky-Hennion, Bertrand Dubus, Marianne Sagnard, Thierry Laroche, Sylvain Ballandras, Charles Croenne
  • Patent number: 11881429
    Abstract: A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 23, 2024
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11876073
    Abstract: A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: January 16, 2024
    Assignee: SOITEC
    Inventor: David Sotta
  • Patent number: 11876015
    Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 16, 2024
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Franck Colas
  • Patent number: 11877514
    Abstract: A process for producing a crystalline layer of PZT material, comprising the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material, followed by epitaxial growth of the crystalline layer of PZT material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 16, 2024
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11876020
    Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 16, 2024
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Ludovic Ecarnot, Nicolas Daval, Bich-Yen Nguyen, Guillaume Besnard
  • Patent number: 11870411
    Abstract: A process for fabricating a substrate for a radiofrequency device by joining a piezoelectric layer to a carrier substrate by way of an electrically insulating layer, the piezoelectric layer having a rough surface at its interface with the electrically insulating layer, the process being characterized in that it comprises the following steps: —providing a piezoelectric substrate having a rough surface for reflecting a radiofrequency wave, —depositing a dielectric layer on the rough surface of the piezoelectric substrate, —providing a carrier substrate, —depositing a photo-polymerizable adhesive layer on the carrier substrate, —bonding the piezoelectric substrate to the carrier substrate by way of the dielectric layer and of the adhesive layer, in order to form an assembled substrate, —irradiating the assembled substrate with a light flux in order to polymerize the adhesive layer, the adhesive layer and the dielectric layer together forming the electrically insulating layer.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 9, 2024
    Assignee: SOITEC
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 11855120
    Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 ?m is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 26, 2023
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Oleg Kononchuk, Ludovic Ecarnot, Christelle Michau
  • Patent number: 11837463
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: December 5, 2023
    Assignee: SOITEC
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Patent number: 11828000
    Abstract: A process for producing a monocrystalline layer of LNO material comprises the transfer of a monocrystalline seed layer of YSZ material to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of LNO material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 28, 2023
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11800803
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a first free surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer, wherein the useful layer comprises an area of nanocavities.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 24, 2023
    Assignee: SOITEC
    Inventor: Marcel Broekaart
  • Patent number: 11776843
    Abstract: A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 3, 2023
    Assignee: Soitec
    Inventors: Didier Landru, Bruno Ghyselen
  • Patent number: 11742233
    Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventors: Marcel Broekaart, Ionut Radu, Didier Landru
  • Patent number: 11744154
    Abstract: A method for transferring a piezoelectric layer from a donor substrate onto a support substrate comprises the steps of: a) providing a predetermined splitting area in a piezoelectric donor substrate, b) attaching the piezoelectric donor substrate to a support substrate to form an assembly, and c) detaching the piezoelectric layer from the piezoelectric donor substrate comprising applying an electric field. By using the electric field, the detachment step can be carried out at low temperatures. A detachment chamber for carrying out at least a portion of such a method includes one or two chucks comprising first and/or second electrodes for applying an electric field to a piezoelectric layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventor: Cédric Charles-Alfred
  • Patent number: 11742817
    Abstract: A process for transferring a thin layer consisting of a first material to a support substrate consisting of a second material having a different thermal expansion coefficient, comprises providing a donor substrate composed of an assembly of a thick layer formed of the first material and of a handle substrate having a thermal expansion coefficient similar to that of the support substrate, and the donor substrate having a main face on the side of the thick layer introducing light species into the thick layer to generate a plane of weakness therein and to define the thin layer between the plane of weakness and the main face of the donor substrate; assembling the main face of the donor substrate with a face of the support substrate; and detachment of the thin layer at the plane of weakness, the detachment comprising application of a heat treatment.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventors: Isabelle Huyet, Cedric Charles-Alfred, Didier Landru, Alexis Drouin
  • Patent number: 11744153
    Abstract: A method for producing a layer of composition AA?BO3, wherein A consists of at least one element selected from the group consisting of: Li, Na, K, Ca, Mg, Ba, Sr, Pb, La, Bi, Y, Dy, Gd, Tb, Ce, Pr, Nd, Sm, Eu, Ho, Zr, Sc, Ag and Tl, and B consists of at least one element selected from the group consisting of: Nb, Ta, Sb, Ti, Zr, Sn, Ru, Fe, V, Sc, C, Ga, Al, Si, Mn, Zr and Tl, is described. The method includes providing a donor substrate of composition ABO3, forming a layer of composition ABO3 by thinning the donor substrate, and exposing the layer of composition ABO3 to a medium containing ions of an element A? belonging to the same list of elements as A, A? being different from A, such that the ions penetrate into the layer of composition ABO3 to form the layer of composition AA?BO3.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11735685
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Soitec
    Inventor: David Sotta
  • Patent number: 11728207
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 15, 2023
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 11711065
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 25, 2023
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk