Patents Assigned to Soitec
  • Patent number: 10957577
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 23, 2021
    Assignee: SOITEC
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 10950491
    Abstract: A useful layer is layered onto a support by a method that includes the steps of forming an embrittlement plane by implanting light elements into a first substrate, so as to form a useful layer between such plane and one surface of the first substrate; applying the support onto the surface of the first substrate so as to form an assembly to be fractured; applying a heat treatment for embrittling the assembly to be fractured; and initiating and propagating a fracture wave into the first substrate along the embrittlement plane. The fracture wave is initiated in a central area of the embrittlement plane and the propagation speed of the wave is controlled so that the velocity thereof is sufficient to cause the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof, if any, are confined to a peripheral area of the useful layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 16, 2021
    Assignees: Soitec, COMMISSARIAT Á L'ÈNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frederic Mazen, Damien Massy, Shay Reboh, Francois Rieutord
  • Patent number: 10943815
    Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms-cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms-cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 9, 2021
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 10943778
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 9, 2021
    Assignee: Soitec
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Patent number: 10924081
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 16, 2021
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 10910256
    Abstract: The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 2, 2021
    Assignee: Soitec
    Inventors: Fabrice Letertre, Oleg Kononchuk
  • Patent number: 10910250
    Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 2, 2021
    Assignee: Soitec
    Inventors: Marcel Broekaart, Ionut Radu, Didier Landru
  • Publication number: 20210028348
    Abstract: A method for separating a removable composite structure using a light flux includes supplying the removable composite structure, which successively comprises: a substrate that is transparent to the light flux; an optically absorbent layer for at least partially absorbing a light flux; a sacrificial layer adapted to dissociate subject to the application of a temperature higher than a dissociation temperature and made of a material different from that of the optically absorbent layer; and at least one layer to be separated. The method further includes applying a light flux through the substrate, the light flux being at least partly absorbed by the optically absorbent layer, so as to heat the optically absorbent layer; heating the sacrificial layer by thermal conduction from the optically absorbent layer, up to a temperature that is greater than or equal to the dissociation temperature; and dissociating the sacrificial layer under the effect of the heating.
    Type: Application
    Filed: March 22, 2019
    Publication date: January 28, 2021
    Applicants: Soitec, Soitec
    Inventors: Jean-Marc Bethoux, Guillaume Besnard, Yann Sinquin
  • Patent number: 10903263
    Abstract: A front-side type image sensor includes a substrate successively comprising a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P? type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 26, 2021
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Publication number: 20210020826
    Abstract: A method for transferring a piezoelectric layer onto a support substrate comprises:—providing a donor substrate including a heterostructure comprising a piezoelectric substrate bonded to a handling substrate, and a polymerized adhesive layer at the interface between the piezoelectric substrate and the handling substrate,—forming a weakened zone in the piezoelectric substrate, so as to delimit the piezoelectric layer to be transferred,—providing the support substrate,—forming a dielectric layer on a main face of the support substrate and/or of the piezoelectric substrate,—bonding the donor substrate to the support substrate, the dielectric layer being at the bonding interface, and—fracturing and separating the donor substrate along the weakened zone at a temperature below or equal to 300° C.
    Type: Application
    Filed: March 21, 2019
    Publication date: January 21, 2021
    Applicant: Soitec
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 10886162
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 5, 2021
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Publication number: 20200389148
    Abstract: The invention relates to a SAW resonator (100) comprising at least: a substrate (102); a layer (108) of piezoelectric material arranged on the substrate; a first attenuation layer (112) arranged between the substrate and the layer of piezoelectric material, and/or, when the substrate comprises at least two different layers (104, 106), a second attenuation layer (114) arranged between the two layers of the substrate; and in which the at least one attenuation layer is/are heterogeneous.
    Type: Application
    Filed: March 9, 2018
    Publication date: December 10, 2020
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thu Trang VO, Jean-Sebastien MOULET, Alexandre REINHARDT, Isabelle HUYET, Alexis DROUIN, Yann SINQUIN
  • Patent number: 10847370
    Abstract: A method for dissolving a buried oxide in a silicon-on-insulator wafer comprises providing a silicon-on-insulator wafer having a silicon layer attached to a carrier substrate via a buried oxide layer, and annealing the silicon-on-insulator wafer to at least partially dissolve the buried oxide layer. The method further comprises a step of providing an oxygen scavenging layer on or over the silicon layer before the annealing step.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 24, 2020
    Assignee: Soitec
    Inventor: Frederic Allibert
  • Patent number: 10826459
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: November 3, 2020
    Assignee: Soitec
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 10819282
    Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 27, 2020
    Assignee: Soitec
    Inventors: Marcel Broekaart, Frederic Allibert, Eric Desbonnets, Jean-Pierre Raskin, Martin Rack
  • Publication number: 20200321243
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: October 8, 2020
    Applicants: Soitec, Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 10777447
    Abstract: A method for determining a suitable implanting energy of at least two atomic species in a donor substrate to create a weakened zone defining a monocrystalline semiconductor layer to be transferred onto a receiver substrate, comprises the following steps: (i) forming a dielectric layer on at least one of the donor substrate and the receiver substrate; (ii) co-implanting the species in the donor substrate; (iii) bonding the donor substrate on the receiver substrate; (iv) detaching the donor substrate along the weakened zone to transfer the monocrystalline semiconductor layer and recover the remainder of the donor substrate; (v) inspecting the peripheral crown of the remainder of the donor substrate, or of the receiver substrate on which the monocrystalline semiconductor layer was transferred at step (iv); (vi) if the crown exhibits zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is too high; (vii) if said the crown does not exhibit zones transferred on
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 15, 2020
    Assignee: Soitec
    Inventors: Ludovic Ecarnot, Nadia Ben Mohammed, Carine Duret
  • Publication number: 20200259069
    Abstract: A method for producing a layer of composition AA?BO3, where A is composed of at least one element selected from: Li, Na, K, Ca, Mg, Ba, Sr, Pb, La, Bi, Y, Dy, Gd, Tb, Ce, Pr, Nd, Sm, Eu, Ho, Zr, Sc, Ag and Tl, and B is composed of at least one element selected from: Nb, Ta, Sb, Ti, Zr, Sn, Ru, Fe, V, Sc, C, Ga, Al, Si, Mn Zr and Tl, wherein the method comprises the steps of: providing a donor substrate of composition ABO3, forming a layer of composition ABO3 by thinning the donor substrate, and, before and/or after the thinning step, exposing the ABO3 layer to a medium containing ions of an element A? belonging to the same list of elements as A, A? being different from A, such that the ions penetrate into the layer to form a layer of composition AA?BO3.
    Type: Application
    Filed: May 24, 2017
    Publication date: August 13, 2020
    Applicant: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 10703627
    Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: July 7, 2020
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ludovic Ecarnot
  • Patent number: 10672646
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 2, 2020
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval