Patents Assigned to Soitec
  • Patent number: 12040424
    Abstract: A process for fabricating a growth substrate comprises preparing a donor substrate by forming a crystalline semiconductor surface layer on a seed layer of a carrier. This preparation comprises forming the surface layer as a plurality of alternations of an InGaN primary layer and of an AlGaN secondary layer, the indium concentration and the thickness of the primary layers and the aluminum concentration and the thickness of the secondary layers being selected so that a homogeneous AlInGaN layer that is equivalent, in terms of concentration of aluminum and indium, to the surface layer has a natural lattice parameter different from the lattice parameter of the seed layer.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: July 16, 2024
    Assignee: Soitec
    Inventors: Jean-Marc Bethoux, Mariia Rozhavskaia
  • Patent number: 12040194
    Abstract: A method for etching a main surface of a thin layer of a substrate, which comprises immersing the substrate in an etching bath so as to expose the main surface to an etching agent, the substrate being oriented relative to the bath such that:—when it is introduced into the bath, the main surface is gradually immersed from an initial introduction point (PII) to an end introduction point (PFI), at an introduction speed, and—when it exits the bath, the main surface gradually emerges from an initial exit point (PIS) to an end exit point (PFS), at an exit speed, the method being characterized in that:—the introduction speed is chosen in such a way as to etch the main surface according to a first non-uniform profile between the initial introduction point (PII) and the end introduction point (PFI), and/or—the exit speed is chosen in such a way as to etch the main surface according to a second non-uniform profile between the initial exit point (PIS) and the end exit point (PFS), in order to compensate for non-uniformi
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: July 16, 2024
    Assignee: Soitec
    Inventors: Laurent Viravaux, Sébastien Carton, Onintza Ros
  • Patent number: 12034068
    Abstract: A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: July 9, 2024
    Assignee: SOITEC BELGIUM
    Inventor: Joff Derluyn
  • Patent number: 12033854
    Abstract: A method for producing a composite silicon carbide structure comprises: providing an initial substrate of monocrystalline silicon carbide; depositing an intermediate layer of polycrystalline silicon carbide at a temperature higher than 1000° C. on the initial substrate, the intermediate layer having a thickness greater than or equal to 1.5 microns; implanting light ionic species through the intermediate layer to form a buried brittle plane in the initial substrate, delimiting the thin layer between the buried brittle plane and the intermediate layer, and depositing an additional layer of polycrystalline silicon carbide at a temperature higher than 1000° C. on the intermediate layer, the intermediate layer and the additional layer forming a carrier substrate, and separating the buried brittle plane during the deposition of the additional layer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 9, 2024
    Assignee: Soitec
    Inventors: Yann Sinquin, Jean-Marc Bethoux, Damien Radisson
  • Publication number: 20240190120
    Abstract: A method for producing a multilayer structure includes the following steps: a) providing a first substrate, b) depositing a thick layer of a precursor formulation including a preceramic polymer filled with inorganic particles on the first substrate, c) providing a second substrate, d) adhesively bonding the thick layer and the second substrate, e) thinning the first substrate or the second substrate so as to obtain an active layer, f) applying a pyrolysis heat treatment so as to ceramize the preceramic polymer of the thick layer and to obtain a ceramic matrix composite material, the filler content and the nature of the inorganic particles being chosen so that the thick layer has a coefficient of thermal expansion which differs, at most, by 15% from that of the first substrate and from that of the second substrate.
    Type: Application
    Filed: April 12, 2022
    Publication date: June 13, 2024
    Applicants: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Marilyne ROUMANIE, Christelle NAVONE, Sébastien QUENARD, Didier LANDRU, Christelle VEYTIZOU
  • Patent number: 12009209
    Abstract: A process for preparing a support comprises the placing of a substrate on a susceptor in a chamber of a deposition system, the susceptor having an exposed surface not covered by the substrate; the flowing of a precursor containing carbon in the chamber at a deposition temperature so as to form at least one layer on an exposed face of the substrate, while at the same time depositing species of carbon and of silicon on the exposed surface of the susceptor. The process also comprises, directly after the removal of the substrate from the chamber, a first etch step consisting of the flowing of an etch gas in the chamber at a first etching temperature not higher than the deposition temperature so as to eliminate at least some of the species of carbon and silicon deposited on the susceptor.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: June 11, 2024
    Assignee: Soitec
    Inventor: Young-Pil Kim
  • Patent number: 12002690
    Abstract: A system for fracturing a plurality of wafer assemblies, one of the wafers of each assembly comprising a plane of weakness and each assembly comprising a peripheral lateral groove comprises: a cradle for keeping the assemblies of the plurality of assemblies spaced apart and parallel to one another, along a storage axis; a separation device for applying separating forces in the peripheral groove of an assembly arranged in a fracture zone of the separating device, the separating force aiming to separate the wafers of the assembly from one another so as to initiate its fracture at the plane of weakness; and a drive device configured to move along the storage axis of the cradle opposite the separating device so as to successively place an assembly of the cradle in the fracture zone of the separation device.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 4, 2024
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 12002697
    Abstract: A method for monitoring a heat treatment applied to a substrate comprising a weakened zone formed by implanting atomic species for splitting the substrate along the weakened zone, the substrate being arranged in a heating chamber, the method comprising recording sound in the interior or in the vicinity of the heating chamber and detecting, in the recording, a sound emitted by the substrate during the splitting thereof along the weakened zone. A device for the heat treatment of a batch of substrates comprises an annealing furnace comprising a heating chamber intended to receive the batch, at least one microphone configured to record sounds in the interior or in the vicinity of the heating chamber, and a processing system configured to detect, in an audio recording produced by the microphone, a sound emitted when a substrate splits.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 4, 2024
    Assignee: Soitec
    Inventors: François Rieutord, Frédéric Mazen, Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed
  • Patent number: 11976380
    Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: May 7, 2024
    Assignee: SOITEC
    Inventor: Bruno Ghyselen
  • Patent number: 11979132
    Abstract: A method for manufacturing a substrate for a radiofrequency filter by joining a piezoelectric layer to a carrier substrate via an electrically insulating layer, wherein the method comprises depositing the electrically insulating layer by spin coating an oxide belonging to the family of SOGs (spin-on glasses) on the surface of the piezoelectric layer to be joined to the carrier substrate, followed by an anneal for densifying the electrically insulating layer before joining the piezoelectric layer to the carrier substrate via the electrically insulating layer.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 7, 2024
    Assignee: Soitec
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 11974505
    Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 30, 2024
    Assignee: Soitec
    Inventors: Frédéric Allibert, Christelle Veytizou
  • Patent number: 11962288
    Abstract: A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: April 16, 2024
    Assignee: Soitec
    Inventors: Eric Michoulier, Sylvain Ballandras, Thierry LaRoche
  • Patent number: 11939214
    Abstract: A method for manufacturing a device comprising a membrane extending over a useful cavity, the method comprising: providing a generic structure comprising a surface layer extending in a main plane and arranged on a first face of a support substrate, the support substrate comprising elementary cavities opening under the surface layer and partitions delimiting each elementary cavity, the partitions having top surfaces that form all or part of the first face of the support substrate; defining a group of adjacent elementary cavities, such that a contour of the group of elementary cavities corresponds, in the main plane, to a contour of the useful cavity; and removing the partitions situated within the contour of the group of elementary cavities, in order to form the useful cavity, and to free the surface layer arranged above the useful cavity and forming the membrane.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: March 26, 2024
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11940407
    Abstract: A microsensor for detecting ions in a fluid, comprises: a field-effect transistor having a source, a drain, an active region between the source and the drain, and a gate disposed above the active region, an active layer, in which the active region is formed, a dielectric layer positioned beneath the active layer, a support substrate disposed under the dielectric layer and comprising at least one buried cavity located plumb with the gate of the field-effect transistor in order to receive the fluid.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: March 26, 2024
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11935743
    Abstract: A process for producing a monocrystalline layer of diamond or iridium material comprises transferring a monocrystalline seed layer of SrTiO3 material onto a carrier substrate of silicon material, followed by epitaxial growth of the monocrystalline layer of diamond or iridium material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 19, 2024
    Assignee: SOITEC
    Inventor: Bruno Ghyselen
  • Patent number: 11936364
    Abstract: A surface acoustic wave device comprising a base substrate, a piezoelectric layer and an electrode layer in between the piezoelectric layer and the base substrate, a comb electrode formed on the piezoelectric layer comprising a plurality of electrode means with a pitch p, defined asp=A, with A being the wavelength of the standing acoustic wave generated by applying opposite potentials to the electrode layer and comb electrode, wherein the piezoelectric layer comprises at least one region located in between the electrode means, in which at least one physical parameter is different compared to the region underneath the electrode means or fingers. A method of fabrication for such surface acoustic wave device is also disclosed. The physical parameter may be thickness, elasticity, doping concentration of Ti or number of protons obtained by proton exchange.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 19, 2024
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Thierry LaRoche
  • Patent number: 11930710
    Abstract: A hybrid structure and a method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a?) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c).
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 12, 2024
    Assignee: SOITEC
    Inventor: Didier Landru
  • Patent number: 11923239
    Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 11913134
    Abstract: A process for manufacturing a two-dimensional film of a group IV material having a hexagonal crystalline structure, in particular, graphene, comprises formation of a growth substrate, comprising the transfer of a single-crystal metal film suitable for the growth of the two-dimensional film on a support substrate, and epitaxial growth of the two-dimensional film on the metal film of the substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: February 27, 2024
    Assignee: SOITEC
    Inventors: Bruno Ghyselen, Jean-Marc Bethoux
  • Patent number: 11901483
    Abstract: An optoelectronic semiconductor structure (SC) comprises an active InGaN-based layer disposed between an n-type injection layer and a p-type injection layer, the active p-type injection layer comprising a first InGaN layer and, disposed on the first layer, a second layer composed of a plurality of AlGaInN elemental layers, each elemental layer having a thickness less than its critical relaxation thickness, two successive elemental layers having different aluminum and/or indium and/or gallium compositions.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 13, 2024
    Assignee: Soitec
    Inventor: Mariia Rozhavskaia