Patents Assigned to Soitec
  • Patent number: 12732157
    Abstract: A surface acoustic wave (SAW) device comprises an interdigitated transducer structure and at least one acoustic wave reflective structure provided on or in an acoustic wave propagating substrate. The interdigitated transducer structure comprises a first material and the at least one acoustic wave reflective structure comprises a second material different from the first material and/or the acoustic wave reflective structure and the interdigitated transducer structure have different geometrical parameters. A sensor comprises a SAW device as described herein, and a method is used for manufacturing a SAW device comprising at least one acoustic wave reflective structure.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: September 8, 2026
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Emilie Courjon, Florent Bernard, Thierry LaRoche, Julien Garcia, Alexandre Clairet
  • Patent number: 12727401
    Abstract: A method of fabricating a polycrystalline silicon carbide carrier substrate involves growing an initial polycrystalline silicon carbide substrate on a seed of graphite or of silicon-carbide. A stiffening carbon film is then formed on a front face of the initial substrate. The initial substrate has, in the plane of its front face, a first average silicon carbide grain size. The seed is then removed, so as to free the back face of the initial substrate, which has, in the plane of its back face, a second average silicon carbide grain size, which is smaller than the first average size. The back face of the initial substrate is then thinned to a thickness for which the initial substrate has, in the plane of its thinned back face, a third average grain size equal to the first average grain size to within ±30%.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: September 1, 2026
    Assignee: Soitec
    Inventors: Hugo Biard, Mélanie Lagrange
  • Patent number: 12727448
    Abstract: A donor substrate for transferring a single-crystal thin layer made of a first material, onto a receiver substrate. The donor substrate comprises: —a buried weakened plane delimiting an upper portion and a lower portion of the donor substrate, —in the upper portion, a first layer, a second layer adjacent to the buried weakened plane, and a stop layer between the first layer and the second layer, the first layer composed of the first material, the stop layer being formed of a second material, —an amorphized sub-portion, made amorphous by ion implantation, having a thickness less than that of the upper portion, and including at least the first layer; the second layer comprising at least one single-crystal sub-layer, adjacent to the buried weakened plane. Two embodiments of a method may be used for transferring a single-crystal thin layer from the donor substrate.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 1, 2026
    Assignees: Soitec, Commissariat À L'énergie Atomique Et Aux Énergies Alternatives
    Inventors: Larry Vincent, Shay Reboh, Lucie Le Van-Jodin, Frédéric Milesi, Ludovic Ecarnot, Gweltaz Gaudin, Didier Landru
  • Patent number: 12715764
    Abstract: A method for manufacturing a structure comprising membranes overhanging cavities, comprises: a) forming cavities opening at a front face of a support substrate, the cavities having a depth and an area, and being spaced apart by a spacing; b) assembling, by way of direct bonding, a donor substrate on the support substrate to seal the cavities under vacuum, the direct bonding being hydrophilic and involving a given number of water monolayers at a contact interface between the substrates; and c) transferring a thin layer from the donor substrate onto the support substrate, the thin layer comprising the membranes. A specific area is defined around each cavity in the plane of the contact interface and is expressed as a function of half of the spacing. The area, the depth of each cavity, and the specific area are defined in step a) to satisfy a particular relationship.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: August 25, 2026
    Assignees: Soitec, Commissariat À L'énergie Atomique Et Aux Énergies
    Inventors: Bruno Ghyselen, Thierry Salvetat, Guillaume Berre, François Rieutord
  • Patent number: 12703929
    Abstract: A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 1019/cm3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 1019/cm3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: August 11, 2026
    Assignee: Soitec
    Inventors: Frédéric Allibert, Eric Guiot
  • Patent number: 12699290
    Abstract: A method for manufacturing a thermo-optic component comprises the following steps: a) providing a silicon-on-insulator (SOI) substrate comprising: a surface layer made of single-crystal silicon, extending in a main plane and placed on a dielectric layer, itself placed on a carrier made of silicon, and at least one buried cavity, which is formed in the carrier and which opens under the dielectric layer, b) forming an optical waveguide extending in the main plane and comprising a core formed in the surface layer and encircled by an optical confinement layer including the dielectric layer, c) producing at least one heating element, on the optical waveguide, the heating element being positioned, in the main plane, plumb with a segment of the optical waveguide, or on either side of the segment, the heating element and the segment of the optical waveguide being located plumb with the at least one buried cavity.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: August 4, 2026
    Assignee: Soitec
    Inventors: Corrado Sciancalepore, Bruno Ghyselen, Alain Delpy, Céline Cailler, David Herisson, Aziz Alamidrissi
  • Patent number: 12685097
    Abstract: A method for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications, comprises: providing a P-doped semiconductor donor substrate; forming a sacrificial layer on the donor substrate; implanting atomic species through the sacrificial layer so as to form in the donor substrate an area of embrittlement defining a thin semiconductor layer that is to be transferred; removing the sacrificial layer from the donor substrate after the implantation; providing a supporting semiconductor substrate having an electrical resistivity greater than or equal to 500 ?·cm; forming an electrically insulating layer on the supporting substrate; bonding the donor substrate on the supporting substrate, the thin semiconductor layer and the electrically insulating layer being at the interface of the bonding; detaching the donor substrate along the area of embrittlement so as to transfer the thin semiconductor layer from the donor substrate onto the supporting substrate.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: July 14, 2026
    Assignee: Soitec
    Inventors: Isabelle Bertrand, Walter Schwarzenbach, Frédéric Allibert
  • Patent number: 12676593
    Abstract: A transducer structure for a surface acoustic device comprises a composite substrate comprising a piezoelectric layer, a pair of inter-digitated comb electrodes, comprising a plurality of electrode means with a pitch p satisfying the Bragg condition, wherein the inter-digitated comb electrodes are embedded in the piezoelectric layer such that, in use, the excitation of a wave propagating mode in the volume of the electrode means is taking place and is the predominant propagating mode of the structure. The present disclosure relates also to an acoustic wave device comprising at least one transducer structure as described above and to a method for fabricating the transducer structure. The present disclosure relates also to the use of the frequency of the bulk wave propagating in the electrode means of the transducer structure in an acoustic wave device to generate contribution at high frequency, in particular, above 3 GHz.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 7, 2026
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Emilie Courjon, Florent Bernard
  • Patent number: 12672526
    Abstract: A method for fabricating a semiconductor-on-insulator substrate for radiofrequency applications, comprises: forming a donor substrate through epitaxial growth of an undoped semiconductor layer on a p-doped semiconductor seed substrate; forming an electrically insulating layer on the undoped epitaxial semiconductor, implanting ion species through the electrically insulating layer, so as to form, in the undoped epitaxial semiconductor layer, a weakened area defining a semiconductor thin layer to be transferred, providing a semiconductor carrier substrate having an electrical resistivity greater than or equal to 500 ?·cm, bonding the donor substrate to the carrier substrate via the electrically insulating layer, and detaching the donor substrate along the weakened area of embrittlement so as to transfer the semiconductor thin layer from the donor substrate to the carrier substrate.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 30, 2026
    Assignee: Soitec
    Inventors: Isabelle Bertrand, Walter Schwarzenbach, Frédéric Allibert
  • Patent number: 12622236
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: May 5, 2026
    Assignee: Soitec
    Inventors: Patrick Reynaud, Marcel Broekaart, Frédéric Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Patent number: 12622189
    Abstract: A method of manufacturing a composite structure comprises: a) providing a donor substrate of a single-crystal semiconductor material, b) implanting ions into the donor substrate, excluding an annular peripheral region, to form a buried brittle plane, the implantation conditions defining a first thermal budget for obtaining bubbling on a face of the donor substrate and a second thermal budget for obtaining a fracture in the brittle plane, c) forming a stiffening film on the donor substrate, carried out by applying a thermal budget lower than the first thermal budget, the stiffening film being perforated in the form of a mesh, the perforated stiffening film leaving a plurality of zones of the front face bare, d) depositing a carrier substrate on the donor substrate carried out by applying a thermal budget greater than the first thermal budget, and e) separating the donor substrate along the brittle plane.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: May 5, 2026
    Assignee: Soitec
    Inventors: Hugo Biard, Didier Landru
  • Patent number: 12617194
    Abstract: A method for producing a multilayer structure includes the following steps: a) providing a first substrate, b) depositing a thick layer of a precursor formulation including a preceramic polymer filled with inorganic particles on the first substrate, c) providing a second substrate, d) adhesively bonding the thick layer and the second substrate, e) thinning the first substrate or the second substrate so as to obtain an active layer, f) applying a pyrolysis heat treatment so as to ceramize the preceramic polymer of the thick layer and to obtain a ceramic matrix composite material, the filler content and the nature of the inorganic particles being chosen so that the thick layer has a coefficient of thermal expansion which differs, at most, by 15% from that of the first substrate and from that of the second substrate.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: May 5, 2026
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Marilyne Roumanie, Christelle Navone, Sébastien Quenard, Didier Landru, Christelle Veytizou
  • Patent number: 12615998
    Abstract: A temporary substrate, which is detachable at a detachment temperature higher than 1000° C. comprises: a semiconductor working layer extending along a main plane, a carrier substrate, an intermediate layer having a thickness less than 20 nm arranged between the working layer and the carrier substrate, a bonding interface located in or adjacent the intermediate layer, gaseous atomic species distributed according to a concentration profile along the axis normal to the main plane, the atoms remaining trapped in the intermediate layer and/or in an adjacent layer of the carrier substrate with a thickness less than or equal to 10 nm and/or in an adjacent sublayer of the working layer with a thickness less than or equal to 10 nm when the temporary substrate is subjected to a temperature lower than the detachment temperature.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 28, 2026
    Assignee: Soitec
    Inventors: Hugo Biard, Gweltaz Gaudin, Séverin Rouchier, Didier Landru
  • Patent number: 12616005
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: April 28, 2026
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Patent number: 12609672
    Abstract: A transducer structure for a surface acoustic device comprises a composite substrate comprising a piezoelectric layer, a pair of inter-digitated comb electrodes, comprising a plurality of electrode means with a pitch p satisfying the Bragg condition, wherein the inter-digitated comb electrodes are embedded in the piezoelectric layer such that, in use, the excitation of a wave propagating mode in the volume of the electrode means is taking place and is the predominant propagating mode of the structure. The present disclosure relates also to an acoustic wave device comprising at least one transducer structure as described above and to a method for fabricating the transducer structure. The present disclosure relates also to the use of the frequency of the bulk wave propagating in the electrode means of the transducer structure in an acoustic wave device to generate contribution at high frequency, in particular, above 3 GHz.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 21, 2026
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Emilie Courjon, Florent Bernard
  • Patent number: 12603629
    Abstract: A composite structure for an acoustic wave device comprising a heterostructure includes: a useful layer of piezoelectric material, having a first face and a second face, the first face being arranged at a first bonding interface on a support substrate having a coefficient of thermal expansion less than that of the useful layer, wherein the composite structure further comprises a functional layer, an entire surface of which is arranged at a second bonding interface on the second face of the useful layer and having a coefficient of thermal expansion less than that of the useful layer. Methods are used for producing such a composite structure.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 14, 2026
    Assignee: Soitec
    Inventors: Pascal Guenard, Ionut Radu, Didier Landru, Eric Desbonnets
  • Patent number: 12598923
    Abstract: A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: —regions of direct contact between the working layer and the carrier substrate; and —agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: April 7, 2026
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Gweltaz Gaudin, Ionut Radu, Franck Fournel, Julie Widiez, Didier Landru
  • Patent number: 12590926
    Abstract: An acoustic wave sensor device comprises a first interdigitated transducer, a first reflection structure, a second reflection structure, a first resonance cavity comprising a first upper surface and formed between the first interdigitated transducer and the first reflection structure, and a second resonance cavity comprising a second upper surface and formed between the first interdigitated transducer and the second reflection structure. At least one of the first and second upper surfaces is covered at least partly by a metalization layer or a passivation layer. The present invention relates also to an acoustic wave sensor assembly.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: March 31, 2026
    Assignee: Soitec
    Inventors: Sylvain Ballandras, Thierry LaRoche, Julien Garcia, Emilie Courjon
  • Patent number: 12590854
    Abstract: A resonator device for measuring stress comprises at least two resonators, each resonator comprising an inter-digitated transducer structure arranged between two reflecting structures on or in a piezoelectric substrate, wherein the at least two resonators are arranged and positioned such that they have two different wave propagation directions, and each resonator comprises at least two parts with the area between the two parts of the at least two resonators forming a cavity, wherein the cavity is shared by the at least two resonators and wherein for at least one resonator, in particular, all resonators, the inter-digitated transducer structure comprises a first material and the reflecting structures a second material different from the first material and/or the inter-digitated transducer structure and the reflecting structures have different geometrical parameters. A differential sensing device comprises at least one resonator device as described herein.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 31, 2026
    Assignee: Soitec
    Inventors: Emilie Courjon, Florent Bernard, Thierry LaRoche, Julien Garcia, Alexandre Clairet, Sylvain Ballandras
  • Patent number: 12588250
    Abstract: An NCFET transistor comprises a semiconductor-on-insulator substrate for a field-effect transistor, and the NCFET transistor successively comprises, from its base to its surface: a semiconductor carrier substrate; a single ferroelectric layer, arranged in direct contact with the carrier substrate, which layer is designed to be biased so as to form a negative capacitance; and an active layer of a semiconductor material, which layer is designed to form the channel of the transistor, and is arranged in direct contact with the ferroelectric layer. The NCFET transistor further comprises a channel that is arranged in the active layer, a source and a drain that are arranged in the active layer on either side of the channel, and a gate that is arranged on the channel and is insulated from the channel by a gate dielectric.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: March 24, 2026
    Assignee: Soitec
    Inventors: Ionut Radu, Guillaume Besnard, Sorin Cristoloveanu