Patents Assigned to Soitec
  • Patent number: 11837463
    Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: December 5, 2023
    Assignee: SOITEC
    Inventors: Pascal Guenard, Marcel Broekaart, Thierry Barge
  • Patent number: 11828000
    Abstract: A process for producing a monocrystalline layer of LNO material comprises the transfer of a monocrystalline seed layer of YSZ material to a carrier substrate of silicon material followed by epitaxial growth of the monocrystalline layer of LNO material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 28, 2023
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11800803
    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a first free surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer, wherein the useful layer comprises an area of nanocavities.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 24, 2023
    Assignee: SOITEC
    Inventor: Marcel Broekaart
  • Patent number: 11776843
    Abstract: A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 3, 2023
    Assignee: Soitec
    Inventors: Didier Landru, Bruno Ghyselen
  • Patent number: 11742817
    Abstract: A process for transferring a thin layer consisting of a first material to a support substrate consisting of a second material having a different thermal expansion coefficient, comprises providing a donor substrate composed of an assembly of a thick layer formed of the first material and of a handle substrate having a thermal expansion coefficient similar to that of the support substrate, and the donor substrate having a main face on the side of the thick layer introducing light species into the thick layer to generate a plane of weakness therein and to define the thin layer between the plane of weakness and the main face of the donor substrate; assembling the main face of the donor substrate with a face of the support substrate; and detachment of the thin layer at the plane of weakness, the detachment comprising application of a heat treatment.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventors: Isabelle Huyet, Cedric Charles-Alfred, Didier Landru, Alexis Drouin
  • Patent number: 11742233
    Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventors: Marcel Broekaart, Ionut Radu, Didier Landru
  • Patent number: 11744154
    Abstract: A method for transferring a piezoelectric layer from a donor substrate onto a support substrate comprises the steps of: a) providing a predetermined splitting area in a piezoelectric donor substrate, b) attaching the piezoelectric donor substrate to a support substrate to form an assembly, and c) detaching the piezoelectric layer from the piezoelectric donor substrate comprising applying an electric field. By using the electric field, the detachment step can be carried out at low temperatures. A detachment chamber for carrying out at least a portion of such a method includes one or two chucks comprising first and/or second electrodes for applying an electric field to a piezoelectric layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventor: Cédric Charles-Alfred
  • Patent number: 11744153
    Abstract: A method for producing a layer of composition AA?BO3, wherein A consists of at least one element selected from the group consisting of: Li, Na, K, Ca, Mg, Ba, Sr, Pb, La, Bi, Y, Dy, Gd, Tb, Ce, Pr, Nd, Sm, Eu, Ho, Zr, Sc, Ag and Tl, and B consists of at least one element selected from the group consisting of: Nb, Ta, Sb, Ti, Zr, Sn, Ru, Fe, V, Sc, C, Ga, Al, Si, Mn, Zr and Tl, is described. The method includes providing a donor substrate of composition ABO3, forming a layer of composition ABO3 by thinning the donor substrate, and exposing the layer of composition ABO3 to a medium containing ions of an element A? belonging to the same list of elements as A, A? being different from A, such that the ions penetrate into the layer of composition ABO3 to form the layer of composition AA?BO3.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 29, 2023
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11735685
    Abstract: A method for preparing a crystalline semiconductor layer in order for the layer to be provided with a specific lattice parameter involves a relaxation procedure that is applied for a first time to a first start donor substrate in order to obtain a second donor substrate. Using the second donor substrate as the start donor substrate, the relaxation procedure is repeated for a number of times that is sufficient for the lattice parameter of the relaxed layer to be provided with the specific lattice parameter. A set of substrates may be obtained by the method.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Soitec
    Inventor: David Sotta
  • Patent number: 11728207
    Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 15, 2023
    Assignee: Soitec
    Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
  • Patent number: 11711065
    Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 25, 2023
    Assignee: Soitec
    Inventors: Marcel Broekaart, Thierry Barge, Pascal Guenard, Ionut Radu, Eric Desbonnets, Oleg Kononchuk
  • Patent number: 11706989
    Abstract: A design process is used for designing a device comprising a plurality of micro-machined elements, each comprising a flexible membrane, the elements being arranged in a plane in a determined topology. The design process comprises a step of defining the determined topology so that it has a character compatible with a generic substrate having cavities, the characteristics of which are pre-established. Each flexible membrane of the micro-machined elements is associated with one cavity of the generic substrate. The present disclosure also relates to a fabrication process for fabricating a device comprising a plurality of micro-machined elements, and to this device itself, wherein only some of the pairs of cavities and flexible membranes are configured to form a set of functional micro-machined elements.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 18, 2023
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11688627
    Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 27, 2023
    Assignee: Soitec
    Inventors: Frederic Allibert, Christelle Veytizou, Damien Radisson
  • Patent number: 11670540
    Abstract: Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: June 6, 2023
    Assignees: Soitec, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frédéric Mazen, Damien Massy, Shay Reboh, François Rieutord
  • Patent number: 11652464
    Abstract: A production method for a surface acoustic wave device comprises the following steps: a step of providing a piezoelectric substrate comprising a transducer arranged on the main front face; a step of depositing a dielectric encapsulation layer on the main front face of the piezoelectric substrate and on the transducer; and a step of assembling the dielectric encapsulation layer with the main front face of a support substrate having a coefficient of thermal expansion less than that of the piezoelectric substrate. In additional embodiments, a surface acoustic wave device comprises a layer of piezoelectric material equipped with a transducer on a main front face, arranged on a substrate support of which the coefficient of thermal expansion is less than that of the piezoelectric material. The transducer is arranged in a dielectric encapsulation layer, between the layer of piezoelectric material and the support substrate.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 16, 2023
    Assignee: Soitec
    Inventors: Pascal Guenard, Ionut Radu
  • Patent number: 11637542
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 25, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 11626319
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: April 11, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Patent number: 11600766
    Abstract: A method for manufacturing a monocrystalline piezoelectric material layer includes providing a donor substrate made of the piezoelectric material, providing a receiving substrate, transferring a so-called “seed layer” of the donor substrate onto the receiving substrate, and using epitaxy of the piezoelectric material on the seed layer until the desired thickness for the monocrystalline piezoelectric layer is obtained.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 7, 2023
    Assignee: Soitec
    Inventors: Bruno Ghyselen, Ionut Radu, Jean-Marc Bethoux
  • Patent number: 11595020
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 28, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 11595021
    Abstract: The invention relates to a SAW resonator (100) comprising at least: a substrate (102); a layer (108) of piezoelectric material arranged on the substrate; a first attenuation layer (112) arranged between the substrate and the layer of piezoelectric material, and/or, when the substrate comprises at least two different layers (104, 106), a second attenuation layer (114) arranged between the two layers of the substrate; and in which the at least one attenuation layer is/are heterogeneous.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 28, 2023
    Assignees: COMMISSARIAT A L'ENERGIE AT TOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thu Trang Vo, Jean-Sebastien Moulet, Alexandre Reinhardt, Isabelle Huyet, Alexis Drouin, Yann Sinquin