Patents Assigned to Soitec
  • Patent number: 11670540
    Abstract: Substrates may include a useful layer affixed to a support substrate. A surface of the useful layer located on a side of the useful layer opposite the support substrate may include a first region and a second region. The first region may have a first surface roughness, may be located proximate to a geometric center of the surface, and may occupy a majority of an area of the surface. The second region may have a second, higher surface roughness, may be located proximate to a periphery of the surface, and may occupy a minority of the area of the surface.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: June 6, 2023
    Assignees: Soitec, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Didier Landru, Nadia Ben Mohamed, Oleg Kononchuk, Frédéric Mazen, Damien Massy, Shay Reboh, François Rieutord
  • Patent number: 11652464
    Abstract: A production method for a surface acoustic wave device comprises the following steps: a step of providing a piezoelectric substrate comprising a transducer arranged on the main front face; a step of depositing a dielectric encapsulation layer on the main front face of the piezoelectric substrate and on the transducer; and a step of assembling the dielectric encapsulation layer with the main front face of a support substrate having a coefficient of thermal expansion less than that of the piezoelectric substrate. In additional embodiments, a surface acoustic wave device comprises a layer of piezoelectric material equipped with a transducer on a main front face, arranged on a substrate support of which the coefficient of thermal expansion is less than that of the piezoelectric material. The transducer is arranged in a dielectric encapsulation layer, between the layer of piezoelectric material and the support substrate.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 16, 2023
    Assignee: Soitec
    Inventors: Pascal Guenard, Ionut Radu
  • Patent number: 11637542
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 25, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 11626319
    Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: April 11, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Oleg Kononchuk
  • Patent number: 11600766
    Abstract: A method for manufacturing a monocrystalline piezoelectric material layer includes providing a donor substrate made of the piezoelectric material, providing a receiving substrate, transferring a so-called “seed layer” of the donor substrate onto the receiving substrate, and using epitaxy of the piezoelectric material on the seed layer until the desired thickness for the monocrystalline piezoelectric layer is obtained.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 7, 2023
    Assignee: Soitec
    Inventors: Bruno Ghyselen, Ionut Radu, Jean-Marc Bethoux
  • Patent number: 11595020
    Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 28, 2023
    Assignee: Soitec
    Inventors: Arnaud Castex, Daniel Delprat, Bernard Aspar, Ionut Radu
  • Patent number: 11595021
    Abstract: The invention relates to a SAW resonator (100) comprising at least: a substrate (102); a layer (108) of piezoelectric material arranged on the substrate; a first attenuation layer (112) arranged between the substrate and the layer of piezoelectric material, and/or, when the substrate comprises at least two different layers (104, 106), a second attenuation layer (114) arranged between the two layers of the substrate; and in which the at least one attenuation layer is/are heterogeneous.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 28, 2023
    Assignees: COMMISSARIAT A L'ENERGIE AT TOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thu Trang Vo, Jean-Sebastien Moulet, Alexandre Reinhardt, Isabelle Huyet, Alexis Drouin, Yann Sinquin
  • Patent number: 11557715
    Abstract: A method for manufacturing a film, notably monocrystalline, on a flexible sheet, comprises the following steps: providing a donor substrate, forming an embrittlement zone in the donor substrate so as to delimit the film, forming the flexible sheet by deposition over the surface of the film, and detaching the donor substrate along the embrittlement zone so as to transfer the film onto the flexible sheet.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 17, 2023
    Assignee: Soitec
    Inventors: Bruno Ghyselen, Jean-Marc Bethoux
  • Patent number: 11549195
    Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventor: Bruno Ghyselen
  • Patent number: 11552123
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 11542155
    Abstract: A method is used to prepare the remainder of a donor substrate, from which a layer has been removed by delamination in a plane weakened by ion implantation. The remainder comprises, on a main face, an annular step corresponding to a non-removed part of the donor substrate. The method comprises the deposition of a smoothing oxide on the main face of the remainder in order to fill the inner space defined by the annular step and to cover at least part of the annular step, as well as heat treatment for densification of the smoothing oxide. A substrate is produced by the method, and the substrate may be used in subsequent processes.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: January 3, 2023
    Assignee: Soitec
    Inventors: Charlotte Drazek, Djamel Belhachemi
  • Patent number: 11508578
    Abstract: A process for preparing a support comprises the placing of a substrate on a susceptor in a chamber of a deposition system, the susceptor having an exposed surface not covered by the substrate; the flowing of a precursor containing carbon in the chamber at a deposition temperature so as to form at least one layer on an exposed face of the substrate, while at the same time depositing species of carbon and of silicon on the exposed surface of the susceptor. The process also comprises, directly after the removal of the substrate from the chamber, a first etch step consisting of the flowing of an etch gas in the chamber at a first etching temperature not higher than the deposition temperature so as to eliminate at least some of the species of carbon and silicon deposited on the susceptor.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 22, 2022
    Assignee: Soitec
    Inventor: Young-Pil Kim
  • Patent number: 11501997
    Abstract: A layer transfer process comprises depositing a first, temporary bonding layer of SOG comprising methylsiloxane by spin coating on a surface comprising substantially no silicon of an initial substrate, and applying a first heat treatment for densifying the first, temporary bonding layer. An intermediate substrate is joined to the initial substrate, and then thinned A second bonding layer of SOG comprising silicate or methylsilsesquioxane is deposited by spin coating on a surface of the thinned initial substrate and/or a final substrate, and a second heat treatment is applied for densifying the second bonding layer. The thinned initial substrate and the final substrate and then joined, and the intermediate substrate is detached thereafter. The process may be carried out at temperatures below 300° C. to avoid damaging components that may be present in the substrates.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: November 15, 2022
    Assignee: Soitec
    Inventor: Djamel Belhachemi
  • Patent number: 11502428
    Abstract: A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: November 15, 2022
    Assignee: Soitec
    Inventors: Eric Desbonnets, Bernard Aspar
  • Patent number: 11476153
    Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: October 18, 2022
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 11469367
    Abstract: A method for separating a removable composite structure using a light flux includes supplying the removable composite structure, which successively comprises: a substrate that is transparent to the light flux; an optically absorbent layer for at least partially absorbing a light flux; a sacrificial layer adapted to dissociate subject to the application of a temperature higher than a dissociation temperature and made of a material different from that of the optically absorbent layer; and at least one layer to be separated. The method further includes applying a light flux through the substrate, the light flux being at least partly absorbed by the optically absorbent layer, so as to heat the optically absorbent layer; heating the sacrificial layer by thermal conduction from the optically absorbent layer, up to a temperature that is greater than or equal to the dissociation temperature; and dissociating the sacrificial layer under the effect of the heating.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 11, 2022
    Assignee: Soitec
    Inventors: Jean-Marc Bethoux, Guillaume Besnard, Yann Sinquin
  • Patent number: 11462676
    Abstract: A method for adjusting the stress state of a piezoelectric film having a first stress state at room temperature includes a step of forming an assembly including a carrier having a thermal expansion coefficient, a compliant layer placed on the carrier, and the piezoelectric film placed on the compliant layer, the piezoelectric film having a thermal expansion coefficient different from that of the carrier. The method also includes a step of heat treating the assembly, in which the assembly is heated to a treatment temperature above the glass transition temperature of the compliant layer. The present disclosure also relates to a process for fabricating an acoustic wave device comprising the piezoelectric layer the stress state of which was adjusted as described herein.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 4, 2022
    Assignee: Soitec
    Inventors: Jean-Marc Bethoux, Yann Sinquin, Damien Radisson
  • Publication number: 20220298007
    Abstract: A method for sealing cavities using membranes, the method including a) forming cavities arranged in a matrix, of a depth p, a characteristic dimension a, and spaced apart by a spacing b; and b) forming membranes, sealing the cavities, by transferring a sealing film. The method further includes a step a1), executed before step b), of forming a first contour on the front face and/or on the sealing face, the first contour comprising a first trench having a width L and a first depth p1, the formation of the first contour being executed such that after step b) the cavities are circumscribed by the first contour, said first contour being at a distance G from the cavities between one-fifth of b and five b.
    Type: Application
    Filed: August 18, 2020
    Publication date: September 22, 2022
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SOITEC
    Inventors: Thierry SALVETAT, Bruno GHYSELEN, Lamine BENAISSA, Caroline COUTIER, Gweltaz GAUDIN
  • Patent number: 11430910
    Abstract: An engineered substrate comprises: a seed layer made of a first semiconductor material for growth of a solar cell; a support substrate comprising a base and a surface layer epitaxially grown on a first side of the base, the base and the surface layer made of a second semiconductor material; a direct bonding interface between the seed layer and the surface layer; wherein a doping concentration of the surface layer is higher than a predetermined value such that the electrical resistivity at the direct bonding interface is below 10 mOhm·cm2, preferably below 1 mOhm·cm2; and wherein a doping concentration of the base as well as the thickness of the engineered substrate are such that absorption of the engineered substrate is less than 20%, preferably less than 10%, and total area-normalized series resistance of the engineered substrate is less than 10 mOhm·cm2, preferably less than 1 mOhm·cm2.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 30, 2022
    Assignee: Soitec
    Inventors: Cécile Aulnette, Frank Dimroth, Eduard Oliva
  • Patent number: RE49365
    Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventors: Oleg Kononchuk, William Van Den Daele, Eric Desbonnets