Patents Assigned to Soitec
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Publication number: 20120098033Abstract: The invention relates to a process for fabricating a heterostructure. This process is noteworthy in that it comprises the following steps: a) a strained crystalline thin film is deposited on, or transferred onto, an intermediate substrate; b) a strain relaxation layer, made of crystalline material capable of being plastically deformed by a heat treatment at a relaxation temperature at which the material constituting the thin film deforms by elastic deformation is deposited on the thin film; c) the thin film and the relaxation layer are transferred onto a substrate; and d) a thermal budget is applied at at least the relaxation temperature, so as to cause the plastic deformation of the relaxation layer and the at least partial relaxation of the thin film by elastic deformation, and thus to obtain the final heterostructure.Type: ApplicationFiled: December 30, 2011Publication date: April 26, 2012Applicant: SOITECInventor: Bruce Faure
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Publication number: 20120100691Abstract: The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.Type: ApplicationFiled: December 30, 2011Publication date: April 26, 2012Applicant: SoitecInventor: Bruce Faure
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Patent number: 8163570Abstract: A method of initiating molecular bonding, comprising bringing one face of a first wafer to face one face of a second wafer and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example, using a bearing element of a tool, of a mechanical pressure in the range from 0.1 MPa to 33.3 MPa.Type: GrantFiled: August 6, 2009Date of Patent: April 24, 2012Assignee: SoitecInventors: Arnaud Castex, Marcel Broekaart
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Patent number: 8158013Abstract: The invention relates to a process for bonding by molecular adhesion of two substrates to one another during which the surfaces of the substrates are placed in close contact and bonding occurs by propagation of a bonding front between the substrates. The invention includes, prior to bonding, a step of modifying the surface state of one or both of the surfaces of the substrates so as to regulate the propagation speed of the bonding front. The surface can be modified by locally or uniformly heating or roughening the surface(s) of the substrate(s).Type: GrantFiled: June 23, 2009Date of Patent: April 17, 2012Assignee: SoitecInventors: Sebastien Kerdiles, Carine Duret, Alexandre Vaufredaz, Frédéric Metral
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Patent number: 8158487Abstract: The invention relates to a process for annealing a structure that includes at least one wafer, with the annealing process including conducting a first annealing of the structure in an oxidizing atmosphere while holding the structure in contact with a holder in a first position in order to oxidize at least portion of the exposed surface of the structure, shifting the structure on the holder into a second position in which non-oxidized regions of the structure are exposed, and conducting a second annealing of the structure in an oxidizing atmosphere while holding the structure in the second position. The process provides an oxide layer on the structure.Type: GrantFiled: January 21, 2011Date of Patent: April 17, 2012Assignee: SoitecInventors: Nicolas Sousbie, Bernard Aspar, Thierry Barge, Chrystelle Lagahe Blanchard
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Publication number: 20120085400Abstract: Methods of fabricating photovoltaic devices include forming a plurality of subcells in a vertically stacked arrangement on the semiconductor material, each of the subcells being formed at a different temperature than an adjacent subcell such that the adjacent subcells have differing effective band-gaps. The methods of fabricating also include inverting the structure, attaching another substrate to the second semiconductor material, and removing the substrate. For example, each of the subcells may comprise a III-nitride material, and each subsequent subcell may include an indium content different than the adjacent subcell. Novel structures may be formed using such methods.Type: ApplicationFiled: May 26, 2010Publication date: April 12, 2012Applicant: SOITECInventors: Chantal Arena, Heather McFelea
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Patent number: 8153536Abstract: This invention provides apparatus, protocols, and methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a device for moving wafers or substrates that can bath a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.Type: GrantFiled: November 12, 2008Date of Patent: April 10, 2012Assignee: SoitecInventors: Michael Albert Tischler, Ronald Thomas Bertram, Jr.
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Patent number: 8153504Abstract: The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate onto a second semiconducting substrate, characterized in that the process includes, before bonding, the formation of a bonding layer between the first and the second substrate, the bonding layer comprising a plurality of islands distributed over a surface of the first substrate in a determined pattern and separated from one another by regions of a different type, which are distributed in a complementary pattern, wherein the islands are formed via a plasma treatment of the material of the first substrate.Type: GrantFiled: March 26, 2008Date of Patent: April 10, 2012Assignee: SoitecInventors: Frederic Allibert, Sebastien Kerdiles
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Patent number: 8154022Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.Type: GrantFiled: October 26, 2010Date of Patent: April 10, 2012Assignee: SoitecInventors: Chantal Arena, Fabrice Letertre
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Patent number: 8153500Abstract: A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The bonding layer is formed by low pressure chemical vapor deposition (LPCVD) of a layer of silicon oxide on the bonding face of the support substrate or on the bonding face of the thin film. The thin film has a thickness of 5 micrometers or less while the thickness of the layer of oxide is equal to or greater than the thickness of the thin film. The method also includes a heat treatment carried out at a temperature that is higher than the temperature for deposition of the layer of oxide of silicon and for a predetermined period.Type: GrantFiled: January 6, 2009Date of Patent: April 10, 2012Assignee: SoitecInventors: Bruce Faure, Alexandra Marcovecchio
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Patent number: 8148242Abstract: A method for manufacturing a SeOI substrate that includes a thin working layer made from one or more semiconductor material(s); a support layer; and a thin buried oxide layer between the working layer and the support layer. The method includes a manufacturing step of an intermediate SeOI substrate having a buried oxide layer with a thickness greater than a thickness desired for the thin buried oxide layer; and a dissolution step of the buried oxide layer in order to form therewith the thin buried oxide layer. After the dissolution step, an oxidation step of the substrate is conducted for creating an oxidized layer on the substrate, and an oxide migration step for diffusing at least a part of the oxide layer through the working layer in order to increase the electrical interface quality of the substrate and decrease its Dit value.Type: GrantFiled: February 20, 2008Date of Patent: April 3, 2012Assignee: SoitecInventors: Oleg Kononchuk, George K. Celler
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Patent number: 7300853Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.Type: GrantFiled: June 2, 2004Date of Patent: November 27, 2007Assignee: SoitecInventors: Jean-Pierre Joly, Michel Bruel, Claude Jaussaud
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Patent number: 7208392Abstract: A method of creating an electrically conducting bonding between a face of a first semiconductor element and a face of a second semiconductor element using heat treatment. The method applies the faces one against the other with the placing between them of at least one layer of a material configured to provide, after heat treatment, an electrically conducting bonding between the two faces. The deposited layers are chosen so that the heat treatment does not induce any reaction product between said material and the semi-conductor elements. Then, a heat treatment is carried out.Type: GrantFiled: September 7, 2000Date of Patent: April 24, 2007Assignee: SoitecInventors: Claude Jaussaud, Eric Jalaguier, Roland Madar
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Publication number: 20040171232Abstract: A method of detaching a thin film from a source substrate comprises the following steps:Type: ApplicationFiled: November 6, 2003Publication date: September 2, 2004Applicants: CEA, SOITECInventors: Ian Cayrefourcq, Nadia Ben Mohamed, Christelle Lagahe-Blanchard, Nguyet-Phuong Nguyen
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Publication number: 20040166649Abstract: The invention relates to a method of removing a peripheral zone of adhesive while using a layer of adhesive in the process of assembling and transferring a layer of material from a source substrate to a support substrate. The method is remarkable in that it includes bonding the two substrates together by means of a curable adhesive so that an excess of adhesive is present. This assures proper bonding and provides a peripheral zone of adhesive outside of the joined substrates. Only that portion of adhesive is cured which is present in a connection zone between the substrates, and the peripheral zone of non-cured adhesive is removed prior to detaching the transferable layer. The invention is applicable to fabricating a composite substrate in the fields of electronics, opto-electronics, or optics.Type: ApplicationFiled: January 6, 2004Publication date: August 26, 2004Applicant: SOITEC & CEAInventors: Severine Bressot, Olivier Rayssac, Bernard Aspar
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Publication number: 20040161904Abstract: The present invention relates to a method for manufacturing a heterogeneous material structure. The method includes forming a predetermined detachment area in a source substrate, and bonding the source substrate to a handle substrate to form a source-handle structure. The source-handle-structure is then annealed at a first energy level that is lower than the energy of a thermal detachment budget and stopping before detachment of the source substrate. Lastly, the source-handle-structure is annealed at a second energy level that is lower than the first energy level at least until the substrate detaches at the predetermined detachment area.Type: ApplicationFiled: December 10, 2003Publication date: August 19, 2004Applicant: SOITEC & CEAInventors: Cecile Berne, Bruno Ghyselen, Chrystelle Lagahe, Thibaut Maurice
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Patent number: 6372609Abstract: There is provided a method of fabricating an SOI wafer having high quality by hydrogen ion delamination method wherein a damage layer remaining on the surface of the SOI layer after delamination and surface roughness are removed maintaining thickness uniformity of the SOI layer. According to the present invention, there are provided a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after bonding heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after delaminating heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; and an SOI wafer fabricated by the methods.Type: GrantFiled: June 2, 2000Date of Patent: April 16, 2002Assignees: Shin-Etsu Handotai Co., Ltd., Soitec S.A.Inventors: Hiroji Aga, Naoto Tate, Kiyoshi Mitani