Patents Assigned to Soitec
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Patent number: 8247309Abstract: In order to reduce and render uniform the surface roughness and variations in thickness of a layer after detachment (post-fracture) of a donor substrate, the mean temperature of the donor substrate during implantation thereof is controlled so as to be in the range 20° C. to 150° C. with a maximum temperature variation of less than 30° C.Type: GrantFiled: March 26, 2009Date of Patent: August 21, 2012Assignee: SoitecInventors: Sébastien Cattet, Guillaume Cattet-Guerrini, legal representative, Lise Guerrini, legal representative, Nadia Ben Mohamed, Benjamin Scarfogliere
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Patent number: 8241998Abstract: The invention relates to semiconductor-on-insulator structure and its method of manufacture. This structure includes a substrate, a thin, useful surface layer and an insulating layer positioned between the substrate and surface layer. The insulating layer is at least one dielectric layer of a high k material having a permittivity that is higher than that of silicon dioxide and a capacitance that is substantially equivalent to that of a layer of silicon dioxide having a thickness of less than or equal to 30 nm.Type: GrantFiled: January 10, 2008Date of Patent: August 14, 2012Assignee: SoitecInventor: Ian Cayrefourcq
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Patent number: 8241942Abstract: A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.Type: GrantFiled: September 22, 2009Date of Patent: August 14, 2012Assignee: SoitecInventors: Konstantin Bourdelle, Carlos Mazure
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Publication number: 20120199953Abstract: The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length.Type: ApplicationFiled: January 12, 2012Publication date: August 9, 2012Applicant: SOITECInventor: Michel Bruel
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Patent number: 8236593Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.Type: GrantFiled: May 14, 2008Date of Patent: August 7, 2012Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State UniversityInventors: Chantal Arena, Subhash Mahajan, Ilsu Han
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Patent number: 8223582Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.Type: GrantFiled: June 3, 2010Date of Patent: July 17, 2012Assignee: SoitecInventors: Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen
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Patent number: 8216917Abstract: A method for fabricating a substrate of the semiconductor on insulator type by forming an epitaxial layer of semiconducting material on a donor substrate having oxygen precipitates with a density of less than 1010/cm3 or a mean size of less than 500 nm, forming an oxide layer on either a donor or receiver substrate, implanting atomic species in the donor substrate to form a weakened zone in the epitaxial layer, bonding the donor and receiver substrates together, with the oxide layer present at the bonding interface, fracturing the donor substrate in the weakened zone to transfer a layer of the donor substrate to the receiver substrate with the transferred layer including the epitaxial layer, and recycling the remainder of the donor substrate to form a receiver substrate for fabrication of a second semiconductor on insulator type substrate.Type: GrantFiled: January 29, 2009Date of Patent: July 10, 2012Assignee: SoitecInventor: Christophe Maleville
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Patent number: 8216368Abstract: A method of forming an epitaxially grown layer, preferably by providing a region of weakness in a support substrate and transferring a nucleation portion to the support substrate by bonding. A remainder portion of the support substrate is detached at the region of weakness and an epitaxial layer is grown on the nucleation portion. The remainder portion is separated or otherwise removed from the support portion.Type: GrantFiled: September 3, 2009Date of Patent: July 10, 2012Assignee: SoitecInventors: Bruce Faure, Fabrice Letertre
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Patent number: 8212249Abstract: Various structures that include at least one thin layer of an amorphous material on a supporting substrate. One structure generally has a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any end of range point defects. Another structure includes an intermediate substrate having an upper face, an upper portion and a lower portion, an amorphous layer that does not contain end of range point defects, and a first crystalline layer containing end of range point defects subjacent the amorphous layer and located in the lower portion; and a supporting substrate bonded to the upper face of the intermediate substrate. That structure can also contain a weakened zone or porous layer to facilitate removal of the first crystalline layer to provide the amorphous layer as an upper layer of the semiconductor structure.Type: GrantFiled: August 4, 2009Date of Patent: July 3, 2012Assignee: SoitecInventor: Xavier Hebras
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Publication number: 20120164778Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to the peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.Type: ApplicationFiled: June 11, 2010Publication date: June 28, 2012Applicant: SOITECInventors: Chrystelle Lagahe Blanchard, Marcel Broekaart, Arnaud Castex
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Publication number: 20120164843Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Applicant: SOITECInventors: Michael Albert Tischler, Ronald Thomas Bertram, JR.
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Patent number: 8202785Abstract: A method of bonding a first substrate to a second substrate by molecular bonding by forming an insulating layer on the bonding face of the first substrate, chemical-mechanical polishing of the insulating layer, activating a bonding surface of the second substrate by plasma treatment, etching an exposed surface of the insulating layer, and bonding together the two substrates together by molecular bonding wherein the etching is conducted after the chemical-mechanical polishing and before the bonding.Type: GrantFiled: October 27, 2009Date of Patent: June 19, 2012Assignee: SoitecInventors: Arnaud Castex, Gweltaz Gaudin, Marcel Broekaart
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Patent number: 8197597Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.Type: GrantFiled: November 15, 2007Date of Patent: June 12, 2012Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 8198628Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.Type: GrantFiled: March 25, 2008Date of Patent: June 12, 2012Assignee: SoitecInventors: Robert Langer, Hacène Lahreche
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Publication number: 20120132922Abstract: A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction.Type: ApplicationFiled: July 8, 2009Publication date: May 31, 2012Applicant: SOITECInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 8183128Abstract: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate and the insulator layer to a second substrate.Type: GrantFiled: September 19, 2008Date of Patent: May 22, 2012Assignee: SoitecInventors: Nicolas Daval, Sebastien Kerdiles, Cécile Aulnette
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Publication number: 20120118233Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: SOITECInventor: Christiaan J. Werkhoven
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Publication number: 20120112205Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.Type: ApplicationFiled: January 4, 2012Publication date: May 10, 2012Applicant: SOITECInventor: Fabrice Letertre
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Patent number: 8173512Abstract: A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.Type: GrantFiled: April 5, 2011Date of Patent: May 8, 2012Assignee: SoitecInventors: Bruno Ghyselen, Carlos Mazure, Emmanuel Arene
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Publication number: 20120100692Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.Type: ApplicationFiled: January 4, 2012Publication date: April 26, 2012Applicant: SOITECInventor: Fabrice Letertre