Abstract: A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to address values usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle new search data based hash collisions. The H-CAM may optionally also be cascaded.

Abstract: The object of the invention is the coupling of a hydrogen fuel cell to an enzymatic process for the production of electricity and the transformation and sequestration of CO2. Gaseous CO2 emissions from processes such as hydrocarbon reforming are transformed into carbonate or bicarbonate ions and hydrogen ions by the enzymatic system in order to prevent their contribution to the greenhouse effect. The hydrogen ions resulting from the enzymatic process are recovered and combined in order to supply the hydrogen fuel cell. Finally, water, a by-product of the oxidizing reaction of the hydrogen fuel cell, is recovered and recycled back into the aqueous enzymatic system.

Abstract: A triphasic bioreactor for physico-chemically treating a gas is disclosed. The triphasic bioreactor comprises a reaction chamber with a liquid and biocatalysts in suspension in the liquid, for catalyzing a reaction between the gas and the liquid to obtain a treated gas and a solution containing a reaction product. A gas bubbling means is provided in the reaction chamber for bubbling the gas to be treated into the liquid thereby dissolving the gas into the liquid and increasing a pressure inside the reaction chamber. The bioreactor further comprises a liquid inlet in fluid communication with the reaction chamber for receiving the liquid and filling the reaction chamber, a liquid outlet in fluid communication with the reaction chamber for releasing the solution and a gas outlet in fluid communication with the reaction chamber to release the treated gas. The bioreactor further comprises a retention device to retain the biocatalysts in the reaction chamber.

Abstract: A head and neck restraint device, worn by a driver when operating a high performance vehicle, which controls the driver's head from snapping forward and maintains the driver's head, neck and spine in general alignment in the event of a frontal crash. The device includes a pair of anchor straps that are worn along the back of the driver and have first end which connects to the driver's helmet by use of hooks and tethers, and second ends which extends between the driver's legs for connection to a seat belt assembly. A chest strap and a waist strap are attached to the anchor straps for keeping the anchor straps separated at a predetermined distance. When exiting the vehicle, the driver unlatches a standard vehicle seat belt assembly and the restraint device is simultaneously released from the vehicle. Since the restraint is neither rigid nor bulky, the driver can quickly exit the vehicle unrestricted by the device.

Abstract: A chiller tank system for containment of chilled liquids comprises a first tank and a second tank position within the first tank. The first tank is spaced apart from the second tank so that insulation material can be positioned between them The second tank defines a chamber for receiving the liquid to be chilled. A straight-lined, chiller barrel is positioned vertically within the chamber, the chiller barrel defining a bore connected to a flexible, dual hose. The straight-lined chiller barrel extends downward into the tank thereby evenly chilling the liquid to avoid thermal stratification that causes vaporization by creating warm spots within the liquid. A refrigeration unit supplies inert refrigerant to the tank.

Abstract: A treatment unit is disclosed for treating a fluid in continuous mode. This treatment unit provides the opportunity to carry out simultaneously an enzymatic transformation and a capture of a fluid element. The unit has a reservoir with a fluid inlet for receiving a fluid to be treated and a fluid outlet for releasing a treated fluid. The unit also has removable cassettes provided with a reactive material for treating the fluid and two spaced-apart baffle walls in the reservoir for regulating the flow of the fluid therein. The unit further has a reaction chamber defined between each of the two spaced-apart baffles walls. The reaction chamber has an opening for removably inserting therein the cassette. Yet, the unit further has mounting means for mounting the cassette in a reaction chamber spaced-apart from the two baffle walls, whereby a cassette is disposed between two spaced-apart baffle walls and causes the fluid to flow in a zigzag pattern thus further regulating the flow of the fluid.

Abstract: A testing station tests integrated circuits and determines if the integrated circuits pass or fail predefined tests. The integrated circuits are placed in a pass bin if the integrated circuits passed the tests, or a fail bin if the integrated circuits failed the tests. A marking station marks identification information on the integrated circuits in the pass bin. The testing and marking stations are both included in a single, integrated tester-marker system.

Abstract: A system and method for allowing a communication device to accepts voice commands from a user. The voice commands can include commands to execute or dial key sequences or commands to control device functionality. Voice commands are received from a user of the communication device, indicating a command to be carried out by said communication device. The commands are interpreted and executed by the communication device.

Abstract: A modular printer that can be configured to provide different printing sizes, models, and features. The modular printer has a base module that includes base printing electronics, and a drive and print mechanism. Coupled to the base module are different communication modules that provide an interface for the operator of the printer. Different battery modules are designed to interface with the other modular sections.

Abstract: A method is provided for fabricating an array of memory cells for a dynamic random access memory. Each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, a drain and a gate. The source is coupled to a bit line, and the gate is coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of the memory cell transistors. A temporary insulation layer is formed over the lower conductive layer. A portion of the temporary insulation layer and the lower conductive layer are removed to form an electrically separate capacitor bottom plate for each memory cell and an inter-capacitor isolation region. A lateral portion of the temporary insulation layer is removed to form a capacitor sidewall spacing region. A protective layer is formed to fill the inter-capacitor isolation region and the capacitor sidewall spacing region.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A Random Access Memory (RAM) with improved memory access time supporting simultaneous transitions of an address signal and a write enable signal while preventing accidental writes. The RAM includes a memory array, an address transition detector and a race detector. Operation of the memory array is controlled by the address signal and a write clock signal. In response to the write clock's read state the memory array reads data from an address represented by the address signal, while the write clock's write state causes the memory array to write data at the address represented by the address signal. The address transition detector and race detector work together to generate the write clock signal. The address transition detector generates an address transition signal when it detects a transition of the address signal from a representation of a first address of the memory array to a representation of a second address of the memory array.

Abstract: A method is provided for fabricating a stacked capacitor in a storage node (memory cell) of a dynamic random access memory (DRAM) that exceeds the photolithography limit. A DRAM has an array of memory cells and each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, drain and gate. The drain is coupled to a bit line, and the gate coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of each of the memory cell transistors. A protective layer is patterned and formed over a predetermined portion of the lower conductive layer for defining an inter-capacitor isolation region. A portion of the lower conductive layer is removed to form a bottom plate of the capacitor associated with each memory cell, such that a protected portion of the lower conductive layer under the protective layer is removed.

Abstract: A distribution charge pump is disclosed that reduces leakage from a VPP node where a programming voltage (VPP) is provided. The distribution charge pump includes a pump section and a biasing network. The pump section, in response to input signals at 0V or VCC, generates corresponding output signals at 0V or VPP, respectively. Typically, VCC can be between 2V and 5V and VPP can be between 11V and 15V. The pump section includes two n-channel transistors that bootstrap each other to cooperatively pull up the output node to VPP in response to an input signal of VCC. When the charge pump is active, one of the transistors, a native-mode device, transfers charge from the VPP node to an internal node where charge is stored by a capacitor. The biasing network reduces leakage current from the VPP node through the native-mode transistor when the charge pump is inactive.

Abstract: A low voltage charge pump system with a large output voltage range is described. The charge pump system comprises eight charge pump stages, an output stage, and a four phase clock generator. The clock generator generates two sets of four phase shifted signals. The first set of four clock signals are coupled to the first four charge pump stages and have a logic high level of VCC. The second set of clock signals are coupled to the second four charge pump stages and have a logic high level of 2 VCC. Due to the body effect, the negative voltages at the charge pump output stages increases the threshold voltage of a pass transistor which couples the input and output in each charge pump. The larger high voltage level of the second set of clock signals enables the signals to overcome the body effect increased threshold voltages of the pass transistors. The pass transistors are then used to couple negative charge to the next charge pump stage, and positive charge to the preceding charge pump stage.

Abstract: An apparatus and method for minimizing the access time incurred when accessing redundant columns of a dynamic random access memory (DRAM) is herein disclosed. A pair of redundant columns is associated with a defective column. Each pair of redundant columns has a single redundant column decoder that provides access to the column data in the pair of redundant columns. The redundant column decoder is enabled by the column repair circuitry when it receives a column address signal indicating that a defective cell is to be accessed. When a defective column is accessed, the column data from the pair of associated redundant columns is read onto the IO lines as well as the data from the defective column. The three voltages are combined forming an IO signal and the complements of the three voltages are combined forming an IO-BAR signal. The sense amplifier determines the column data value based on the differential between the IO and IO-BAR signals.

Abstract: A high speed memory cell current measurement circuit uses an on-chip reference current circuit that generates a reference current Iref. The reference current circuit includes a first current source transistor. An on-chip current comparison circuit has a second current source transistor that is coupled to the first current source transistor so as to mirror the reference current Iref at a fixed current ratio WR. The current comparison circuit has a current connection path connecting the second current source transistor to a memory cell in the semiconductor memory device whose current is to be compared with Iref/WR. The memory cell is selected from the cells in a memory array using the device's on-chip address decoder circuitry. An on-chip result generation subcircuit, coupled to the current connection path between the second current source transistor and the memory cell, produces a Result signal that indicates whether current flowing through the memory cell is more or less than Iref/WR.

Abstract: The present invention is dynamic pulse generator for generating an output pulse from a first input pulse and a second input pulse, where the output pulse is guaranteed to have a pulse width of at least the pulse width of whichever of the two input pulses has a delayed leading edge with respect to the other. The first input pulse has a first leading edge and a first trailing edge. The second input pulse has a second leading edge and a second trailing edge. The second leading edge is delayed from the first leading edge. An edge detector detects the second leading edge, and outputs a first predetermined level when the second leading edge is detected. The edge detector also detects the first trailing edge and the second trailing edge and outputs a second predetermined level. A latch is responsive to the edge detector and generates a signal indicating that the second leading edge has been detected.

Abstract: Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required.

Abstract: A multibank DRAM memory is described having individual row address strobe bar (RASB) and column address strobe bar (CASB) signals. Logically, only one row can be activated in each memory bank at a time and column access can be performed on one memory bank at a time. A token state machine is used to coordinate column access. In a first embodiment, two banks are utilized having respective asynchronous RASB signals transmitted from an external source. In a second embodiment, N DRAM memory banks are utilized having respective asynchronous internal RASB (IRASB) and internal CASB (ICASB) signals. A global RASB signal and a RASB identifier signal (RID) is used to generate the N IRASB and ICASB signals. The RID signal identifies a particular IRASB signal that is to be generated. The token state machine is operated in a round robin manner. In a third embodiment, the N DRAM memory banks are operated in a synchronous manner.