Abstract: A byte-programmable/byte-erasable flash memory system having on-chip counters and secondary storage for word line and bit line disturbance control during program and erase operations. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits; when the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and the counters are reset. The lifetime of the resulting flash memory system is improved because of decreased erase and program stresses in the memory array.

Abstract: A 5V generator circuit is disclosed that generates a reliable 5V signal for use in integrated circuits from the available VPP or VCC supplies for a wide range of VPP and VCC voltages. When VCC is greater than approximately 4V, the generator circuit generates the 5V signal directly from VCC. When VCC is less than approximately 4V and VPP is greater than approximately 4V but less than about 9V, the generator circuit generates the 5V signal directly from VPP. When VCC is less than approximately 4V and VPP is greater than approximately 9V, the generator produces the 5V signal at approximately half of the voltage level of the VPP signal. When both VCC and VPP are less than about 4V, the 5V signal is generated at the too-low VCC level.

Abstract: A row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry. The row decoder accomplishes this by providing a local decoder having only one input requiring a boosted voltage higher than the power supply voltage. Further, predecoders are used to reduce the number of local decoders that receive the boosted voltage.

Abstract: A voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes. A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. A clock generator outputs at least three non-overlapping phase signals: .phi.1 (which goes high at t1 and low at t6), .phi.2 (which goes high at t3 and low at t4), .phi.3 (which goes low qt t2 and high at t5). The t1 .phi.1 positive transient is AC-coupled to M1's drain, and a smaller fraction of the transient is coupled to M1's gate, precharging M1, which begins to turn-on. The .phi.3 t2 negative transient is AC-coupled to M1's source, increasing M1 gate-source potential, which more fully turns-on M1. The .phi.2 t3 positive transient is coupled to M1's gate, turning-on M1 very hard. A phase clock generator outputting square-wave, same-frequency signals having respective 90.degree.

Abstract: A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to provide additional contacts between Vss metal lines and p+ well taps, all of the source bus regions and the p+ well tap regions being encompassed within a double-well configuration. Depending on the specific embodiment of the present invention, the n+ diffused source bus regions and the nearby p+ well tap may: (a) be separately tied to the Vss metal common source line through separate contact metals (e.g., tungsten plugs); (b) be butted against each other and tied to a common Vss metal source line through separate contact metals; (c) be butted against each other and tied to a common Vss metal source line through a common contact metal (e.g.

Abstract: The Vpp generator for use in a dynamic random access memory has a pump circuit and a voltage regulator. The voltage regulator controls the pump circuit such that the pumped up voltage has a maximum predetermined value. The prior art Vpp regulator sets the pumped up voltage, Vpp, to approximately a supply voltage, Vcc, plus the threshold voltage of a memory cell access transistor. This level becomes very high when the supply voltage, Vcc, is high and may overstress the devices. The present invention regulates the pumped up voltage, Vpp, at a substantially constant voltage level for high supply voltages. This level is safe and will not cause overstress.

Abstract: A write control circuit and method for an asynchronous SRAM that minimizes the write address hold time required to prevent data from being written to incorrect addresses in the memory. The write control circuit temporarily disables a write circuit in the memory whenever the memory address changes. The delay of the write control circuit from input to output is shorter than the delay of a decoder in the memory.

Abstract: A self timed memory address control circuit is described. A Y address signal is pre-decoded and then latched. Address transition detection circuits coupled to X and Y address lines output a pulse to an equalization circuit whenever one of the corresponding address signals change. The WEB address detection circuit outputs a pulse when the WEB signal switches high. When the equalization circuit receives one of these pulses it generates an output pulse to an equalization transistor that is coupled between two local I/O bus lines. The equalization circuit output pulse turns on this transistor to equalize the local I/O bus lines so as to prevent data from being written with them. The equalization circuit also outputs a pulse to a clock generator circuit. The clock generator circuit generates a clock signal which clocks the latch. This causes the latch to couple the pre-decoded output signals to a decoder. The decoder then combines the pre-decoded address signals with other control signals.

Abstract: A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without overwriting the memory addresses for the pending operations. Similarly, data is shifted in the data registers to ensure that data remains available for pending memory access operations. The specific register operations are controlled by a thirteen state state machine. The thirteen states and the relationships between the states are defined to enable the memory controller to perform any combination of read, write and deselect operations without inserting idle cycles.

Abstract: A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer.

Abstract: A programmable memory device includes circuits that permit the selective disabling of certain functions when a battery supply voltage falls below the point necessary to sustain those functions while not disabling other functions of the device capable of working at the lower supply voltage. The programmable memory device includes a controller (422), programmable memory (426), and a voltage monitor (424), and is used in an application having additional circuitry (430). Power is furnished between the main voltage V.sub.CC terminal and the ground GND terminal from an external power source, typically a set of batteries. The voltage monitor enables full extension of the operational voltage range for specific functions of the programmable memory device, or for the application circuitry, or for both by reliably detecting the voltage level of the power source and providing an indication thereof.

Abstract: A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling, local decoder circuitry. The local decoder includes a set of word line drivers, each of which sets the voltage level of a corresponding local word line in response to the voltage levels of its associated global word line and a collection of control signals. Each word line driver includes one p-channel transistor and two n-channel transistors. These three transistors collectively establish selected local word lines at appropriate voltages for erase, program and read operations. The three transistors also establish unselected local word lines at solid bias voltages that prevent disturbance of memory cells that are not the target of a memory operation.

Abstract: An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock terminal to the gate of the pass transistor, and a diode from the transfer stage output to ground. When the transfer stage input goes low, charge is coupled through the resistor to pre-charge the gate of the pass transistor. The resistor has a higher junction breakdown voltage than a transistor which allows the gate of the pass transistor to be driven to a larger voltage.

Abstract: A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessible to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.

Abstract: A tunable phase generator is disclosed suitable for use in integrated circuits. The phase generator includes a delay element wherein passive resistors and conductors are employed to provide relatively constant delays despite changes in operating temperatures and voltages. The phase generator is driven by a clock signal and generates therefrom a self-resettable output signal pulse with a selectable pulse width no longer than the width of the clock signal. The variable widths are provided by varying the delays of the delay elements and adding combinational logic between respective delay elements and at the input and output of the phase generator that ensure that, in most situations, the output signal pulse is reset after a delay that is independent of the pulse width of the clock signal. Delays are lengthened by decreasing the current available to a delay element for charging the capacitors.

Abstract: A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level.

Abstract: A novel driver circuit is disclosed that is used for driving a logic voltage sensed by a sensing amplifier of a memory onto a data line of the memory. The driver circuit is responsive to first sensing signals and second sensing signals that are delayed with respect to the first sensing signals. When the first and second sensing signals indicate that equalization is occuring in the sensing amplifier, the driver circuit latches the data line logic voltage on the data line without any false transitions or glitches occuring on the data line. In addition, the driver circuit becomes self biased when the first sensing signals indicate that sensing is occuring in the sensing amplifier but the second sensing signals indicate that equalization is still occuring. This is done to minimize the voltage swing in the driver circuit when the sensed logic voltage is driven onto the data line while both the first and second sensing signals indicate that sensing is occuring.

Abstract: A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose pulses are out of phase with the clock signals driving the other pumping sections. All of the clock signals have roughly the same frequency. Due to the staggered clocks, each pump is activated during a different respective time period, which smooths out VD.

Abstract: A wordline wakeup circuit for use in a static memory responsive to an external clock signal and chip enable signals provided by a controller/microprocessor to perform a memory operation on the static memory. The wordline wakeup circuit receives a global clock (GCLK) signal generated by memory control circuitry from the external clock signal and a word line enable (WLEN) signal asserted by the control circuitry when the chip enables indicate a pending memory operation. The wordline wakeup circuit asserts a wordline wakeup signal (LWLEN) signal as soon as possible after the GCLK signal goes high. The LWLEN signal when asserted activates decoder circuity to assert wordlines as necessary to perform the memory operation. If the WLEN signal is provided, the wordline wakeup circuit keeps the LWLEN signal high for at least the high portion of the GCLK signal, enabling the decoder to execute the memory operation, if the WLEN signal is not provided, the wordline wakeup circuit drops the LWLEN signal.

Abstract: The present invention provides a high speed, high voltage latch that minimizes leakage current and vulnerability to latch-up. The latch has a switching transistor between a program power supply and the output. The switching transistor is turned off by the latch input when the latch input transitions so as drive the output to a low level. The switching transistor thereby minimizes leakage current. An output driver transistor coupled to the program power supply is used. The latch output is initially pulled up through a Vcc power supply. The output driver transistor turns on after the latch output has been pulled up to an initial level. The output driver transistor then pulls up the output terminal to the high output voltage level through the program power supply. Pulling up the output initially with the Vcc power supply minimizes the device power dissipation. The latch circuit further comprises two program power supplies to prevent latch-up, an n-well power supply and a local power supply.