Abstract: A system for enhancing the separation of particles or fluids from water is disclosed. A settling tank or skim tank is provided with an open submersible acoustophoretic separator. In a skim tank, the separator captures and holds oil droplets or particles, permitting them to coalesce until they are large enough and have sufficient buoyant force to float to the top of the tank. In a settling or sediment tank, separator captures and holds particles until they are large enough that the force of gravity causes them to settle out of the water. The acoustophoretic device thus speeds up separation of the particles or droplets from the water.

Abstract: A method for routing information in a flexible routing network which connects disparate initiators and targets includes implementing a packetization logic at an interface between an initiator or a target and a routing network to receive transmission traffic from the initiator or the target and to packetize the transmission traffic into packets. Each packet includes header and body portions. Each of the header and body portions includes one or more standard sized transmission units. Each standard sized transmission unit includes control and payload sections. A payload section associated with the body portion includes one or more chunks. The method includes encoding the one or more chunks using a Common Data Format (CDF). All transmissions within the routing network are based on the CDF. The CDF facilitates narrow-to-wide and wide-to-narrow link width conversion without having to manipulate subparts of data fields in the transmission traffic.

Abstract: In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: Various methods and apparatuses of protection mechanism are described. A target intellectual property block may field and service requests from an initiator intellectual property block in a system-on-chip network. The target intellectual property block has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block. The request's access is restricted based on access permissions associated with a region within the target intellectual property block and attributes of the request trying to access that region.

Abstract: A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.

Abstract: Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.

Abstract: In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

Abstract: Systems are provided with varying flow chamber configurations which acoustically agglomerate microorganisms such as algae for separation from a host fluid such as water. Related apparatus, systems, techniques and articles are also described.

Abstract: Microorganisms such as microalgae are collected and separated from a host medium such as water. Cellular walls and membranes of the microorganisms are then ruptured to release their lipids using a lipid extraction unit. Thereafter, the lipids from the host medium are collected and separated using a lipid collection and separation unit. Related apparatus, systems, techniques and articles are also described.

Abstract: A system is provided that includes one or more acoustic microfilters through which is flowed a mixture of a fluid and a particulate to selectively filter particles from the fluid. Also included are one or more phononic crystal units coupled to the acoustic microfilter(s) to further selectively filter particles from the fluid. Related apparatus, systems, techniques and articles are also described.

Abstract: A flow chamber is provided through which is flowed a mixture of a fluid and a particulate. The flow chamber comprises at least one multi-phase water inlet through which multi-phase water enters the flow chamber, a water outlet through which water exits the flow chamber, a solids outlet through which particles having a density at or above a pre-defined threshold exit the flow chamber, and a low density outlet through which particles having a density below the pre-defined threshold exit the flow chamber. Also provided are one or more ultrasonic transducers and one or more reflectors corresponding to each transducer to acoustically filter the fluid and cause particles/fluid to be selectively diverted to one of the outlets. Related apparatus, systems, techniques and articles are also described.

Abstract: A damper arrangement is described which provides for selective separation of the insulator compartments from the main body of a wet electrostatic precipitator (WESP), permitting maintenance to be performed on the insulator in the compartment while process gas continues to flow through the WESP.

Abstract: Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A method for providing performance instrumentation and analysis of the electronic design includes defining a first and second set of intended software instrumentation test points and an associated first and second set of performance analysis units. The method further includes instrumenting the first and second sets of software instrumentation test points and the associated first and second sets of performance analysis units to a first model and a second model, respectively. The method further includes creating a first and a second set of software instances associated with the first and second sets of intended software instrumentation test points and associated sets of performance analysis units during run time of a first simulation and a second simulation of the electronic design associated with the first model and second model, respectively.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.

Abstract: Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between initiator intellectual property (IP) cores and target IP cores of the electronic design. A query tool may be configured to format input data to be stored in the defined tables, and have application programming interfaces to retrieve data from the defined tables based on performing a query. The query tool executes an algorithm based on the query to provide the interconnect analysis.

Abstract: Several prototype systems are described for separating oil and water from emulsions. The systems operate at ultrasonic resonance and are thus low power. Each system contains one or more acoustic transducers operating in the 100 kHz to 5 MHz range. Each system contains flow input for the emulsion and two or more flow outputs for the separated oil and water. Existing prototypes operate from 200 mL/min to >15 L/min. Each uses low power in the range of 1-5 W.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.