Abstract: A system is provided that includes one or more acoustic microfilters through which is flowed a mixture of a fluid and a particulate to selectively filter particles from the fluid. Also included are one or more phononic crystal units coupled to the acoustic microfilter(s) to further selectively filter particles from the fluid. Related apparatus, systems, techniques and articles are also described.

Abstract: A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.

Abstract: Provided herein are systems and methods for separation of particulate from water using ultrasonically generated acoustic standing waves.

Abstract: A system is provided that includes one or more acoustic microfilters through which is flowed a mixture of a fluid and a particulate to selectively filter particles from the fluid. Also included are one or more phononic crystal units coupled to the acoustic microfilter(s) to further selectively filter particles from the fluid. Related apparatus, systems, techniques and articles are also described.

Abstract: Microorganisms such as microalgae are collected and separated from a host medium such as water. Cellular walls and membranes of the microorganisms are then ruptured to release their lipids using a lipid extraction unit. Thereafter, the lipids from the host medium are collected and separated using a lipid collection and separation unit. Related apparatus, systems, techniques and articles are also described.

Abstract: A system having improved trapping force for acoustophoresis is described where the trapping force is improved by manipulation of the frequency of the ultrasonic transducer. The transducer includes a ceramic crystal. The crystal may be directly exposed to fluid flow. The crystal may be air backed, resulting in a higher Q factor.

Abstract: Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

Abstract: Maintaining cache coherence in a System-on-a-Chip with both multiple cache coherent master IP cores (CCMs) and non-cache coherent master IP cores (NCMs). A plug-in cache coherence manager (CM), coherence logic in agents, and an interconnect are used for the SoC to provide a scalable cache coherence scheme that scales to an amount of CCMs in the SoC. The CCMs each includes at least one processor operatively coupled through the CM to at least one cache that stores data for that CCM. The CM maintains cache coherence responsive to a cache miss of a cache line on a first cache of the caches, then broadcasts a request for an instance of the data stored corresponding to cache miss of the cache line in the first cache. Each CCM maintains its own coherent cache and each NCM is configured to issue communication transactions into both coherent and non-coherent address spaces.

Abstract: Microorganisms such as microalgae are collected and separated from a host medium such as water. Cellular walls and membranes of the microorganisms are then ruptured to release their lipids using a lipid extraction unit. Thereafter, the lipids from the host medium are collected and separated using a lipid collection and separation unit. Related apparatus, systems, techniques and articles are also described.

Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

Abstract: A system for enhancing the separation of particles or fluids from water is disclosed. A settling tank or skim tank is provided with an open submersible acoustophoretic separator. In a skim tank, the separator captures and holds oil droplets or particles, permitting them to coalesce until they are large enough and have sufficient buoyant force to float to the top of the tank. In a settling or sediment tank, separator captures and holds particles until they are large enough that the force of gravity causes them to settle out of the water. The acoustophoretic device thus speeds up separation of the particles or droplets from the water.

Abstract: A system for removing lipids from blood during cardiopulmonary bypass surgery is disclosed. The system uses an acoustophoretic separator having improved trapping force. The transducer of the acoustophoretic seperator includes a ceramic crystal. Blood flows through the separator, and lipids are trapped and removed.

Abstract: A method for routing information in a flexible routing network which connects disparate initiators and targets includes implementing a packetization logic at an interface between an initiator or a target and a routing network to receive transmission traffic from the initiator or the target and to packetize the transmission traffic into packets. Each packet includes header and body portions. Each of the header and body portions includes one or more standard sized transmission units. Each standard sized transmission unit includes control and payload sections. A payload section associated with the body portion includes one or more chunks. The method includes encoding the one or more chunks using a Common Data Format (CDF). All transmissions within the routing network are based on the CDF. The CDF facilitates narrow-to-wide and wide-to-narrow link width conversion without having to manipulate subparts of data fields in the transmission traffic.

Abstract: In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: Various methods and apparatuses of protection mechanism are described. A target intellectual property block may field and service requests from an initiator intellectual property block in a system-on-chip network. The target intellectual property block has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block. The request's access is restricted based on access permissions associated with a region within the target intellectual property block and attributes of the request trying to access that region.

Abstract: Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.

Abstract: A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.

Abstract: In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.