Abstract: Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

Abstract: Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.

Abstract: Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.

Abstract: Various methods and apparatuses are described in which an interconnect couples to a plurality of initiator network resources and a plurality of target network resources. The interconnect may include a first stage of circuitry, a second stage of circuitry, and an arbitration controller. The first stage of circuitry receives incoming transactions from the plurality of initiator network resources. The second stage of circuitry passes outgoing transactions to the plurality of target network resources connecting to the interconnect. The arbitration controller arbitrates transactions from the plurality of initiator network resources destined to one or more of the target network resources. The target network resources supply their availability to service a transaction to the arbitration controller.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Translation logic couples to the communication fabric. The translation logic implements a higher level protocol layered on top of an underlining protocol and the communication fabric. The translation logic converts one initiator transaction into two or more write transactions and then transmits the write transactions using the underlining protocol of the communication fabric. The translation logic converts the initiator transaction into two or more write transactions and then transmits the write transactions using the underlining protocol of the communication fabric so that the communication fabric does not block or poll for responses, and that data may be transferred in a direction opposite from the initiator transaction request.

Abstract: A method and apparatus of a configurable address mapping and protection architecture and hardware for on-chip systems have been described.

Abstract: A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.

Abstract: A method and apparatus for error handling in networks have been described. The method configures a plurality of cores, wherein each core is connected with and associated with each of one of a plurality of initiators. The method further connects one or more of the initiators to a network. Next, one or more of the initiators determine an error in one or more of the cores and communicate the error.

Abstract: A communication system and method with configurable posting points have been described.

Abstract: The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.

Abstract: Various methods and apparatuses are described in which a software programming interface connects one or more functional checker components and one or more protocol checker components to an interconnect monitor component. A computer readable medium stores code for the one or more functional checker components for Intellectual Property (IP) cores, one or more protocol checker components, the interconnect monitor component, and the software programming interface. The monitor component has code to build data structures containing protocol data types requested by a checker component and code on where to deliver data based upon a particular type of data requested by the checker component.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection. A connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a thread identifier that indicates a transaction stream that the data transfer is part of and a busy signal identified by the thread identifier. The busy signal is issued by the target functional block when resources will be unavailable to perform a transfer.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block communicates a single request fully describing attributes of a two-dimensional data block across the communication fabric to a second functional block capable of decoding the single request to obtain the attributes of the two-dimensional data block. At least one of the functional blocks transmits data associated with the single request across the communication fabric.

Abstract: Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitration controller arbitrates requests for access to a shared resource amongst the plurality of blocks of functionality by implementing an arbitration policy. The arbitration policy groups the transactions from the plurality of blocks of functionality into global groups of transactions for servicing by that shared resource. All of the transactions in a first global group are serviced by that shared resource prior to servicing transactions in a next global group of transactions. The arbitration logic facilitates the arbitration policy. The arbitration logic includes cascaded arbitration units that hierarchically arbitrate for the shared resource.

Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.

Abstract: A method and apparatus for speculative response arbitration to improve system latency have been described.

Abstract: The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.