Patents Assigned to Spansion LLC
  • Publication number: 20140148009
    Abstract: During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: Spansion LLC
    Inventors: Angela Tai Hui, David Matsumoto, Tung-sheng Chen
  • Publication number: 20140148001
    Abstract: Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: Spansion LLC
    Inventors: Chun CHEN, Shenqing Fang
  • Publication number: 20140146606
    Abstract: Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicant: SPANSION LLC
    Inventors: Hagop Nazarian, Richard Fastow
  • Publication number: 20140148010
    Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: Spansion LLC
    Inventor: Angela Tai HUI
  • Publication number: 20140145337
    Abstract: An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines.
    Type: Application
    Filed: December 10, 2013
    Publication date: May 29, 2014
    Applicant: Spansion LLC
    Inventors: Shenqing Fang, Connie WANG, Wen Yu, Fei Wang
  • Patent number: 8735960
    Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 27, 2014
    Assignee: Spansion LLC
    Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Sung Jin Kim, Simon Chan, Ning Cheng
  • Patent number: 8738840
    Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 27, 2014
    Assignee: Spansion LLC
    Inventor: Tzungren Allan Tzeng
  • Publication number: 20140143473
    Abstract: A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: Spansion LLC
    Inventors: Yong K. KIM, Keith H. Wong, Mark A. McClain
  • Publication number: 20140141591
    Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: Spansion LLC
    Inventors: Tung-Sheng CHEN, Shenqing Fang
  • Publication number: 20140138790
    Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: Spansion LLC
    Inventors: Rinji SUGINO, Fei WANG
  • Patent number: 8732360
    Abstract: A storage system and method for storing information in memory nodes. The storage or memory nodes include a communication buffer. Flow of information to the storage nodes is controlled based upon constraints on the communication buffer. In one embodiment, communications between a master controller and a storage node have a determined maximum latency.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: May 20, 2014
    Assignee: Spansion LLC
    Inventors: Roger Dwain Isaac, Seiji Miura
  • Publication number: 20140134332
    Abstract: A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Applicant: Spansion LLC
    Inventor: Rinji SUGINO
  • Patent number: 8725920
    Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: May 13, 2014
    Assignee: Spansion LLC
    Inventor: Clifford Alan Zitlaw
  • Patent number: 8724388
    Abstract: Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 13, 2014
    Assignee: Spansion LLC
    Inventors: Tio Wei Neo, Shivananda Shetty, James Pak
  • Patent number: 8725485
    Abstract: A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: May 13, 2014
    Assignee: Spansion LLC
    Inventors: Masato Tatsuoka, Atsushi Ike
  • Publication number: 20140129218
    Abstract: Computer-based speech recognition can be improved by recognizing words with an accurate accent model. In order to provide a large number of possible accents, while providing real-time speech recognition, a language tree data structure of possible accents is provided in one embodiment such that a computerized speech recognition system can benefit from choosing among accent categories when searching for an appropriate accent model for speech recognition.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: Spansion LLC
    Inventors: Chen Liu, Richard Fastow
  • Publication number: 20140129758
    Abstract: Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: SPANSION LLC
    Inventors: Shinsuke Okada, Yuichi Ise, Daisuke Nakata
  • Publication number: 20140124848
    Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 8, 2014
    Applicant: SPANSION LLC
    Inventors: Minh Q. TRAN, Minh-Van NGO, Alexander H. NICKEL, Jeong-Uk HUH
  • Patent number: 8718571
    Abstract: A transmitting and receiving device includes: a transmission circuit that transmits a signal by FM-modulating a carrier wave of the signal; an FM demodulation circuit that generates a demodulation signal by FM-demodulating the received signal; and a first filter circuit that changes a pass-band for letting the received signal pass through according to the demodulation signal, wherein the transmitting and receiving device perform a power supply line communication through the power supply line in which a signal is transmitted and received among a plurality of the transmitting and receiving devices.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 6, 2014
    Assignee: Spansion LLC
    Inventor: Kazuhiro Tomita
  • Patent number: 8719489
    Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: May 6, 2014
    Assignee: Spansion LLC
    Inventor: Tzungren Tzeng