Patents Assigned to Spansion LLC
  • CHARGE-TRAP NOR WITH SILICON-RICH NITRIDE AS A CHARGE TRAP LAYER
    Publication number: 20140312408
    Abstract: A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT-NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 23, 2014
    Applicant: Spansion LLC
    Inventor: Shenqing FANG
  • SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY
    Publication number: 20140312409
    Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
    Type: Application
    Filed: January 29, 2014
    Publication date: October 23, 2014
    Applicant: SPANSION LLC
    Inventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
  • Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
    Publication number: 20140312465
    Abstract: A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area allowing the die seal area to he disregarded for purposes of calculating a process window.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 23, 2014
    Applicant: Spansion LLC
    Inventor: Fei WANG
  • Non-Volatile memory with silicided bit line contacts
    Patent number: 8866213
    Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 21, 2014
    Assignee: Spansion LLC
    Inventors: Ching-Huang Lu, Simon Siu-Sing Chan, Hidehiko Shiraiwa, Lei Xue
  • Data-processing method, program, and system
    Patent number: 8868822
    Abstract: A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: October 21, 2014
    Assignee: Spansion LLC
    Inventor: Hiroyuki Komori
  • DC-DC Converter With Adaptive Phase Compensation Controller
    Publication number: 20140306752
    Abstract: A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage determined by the output voltage plus said phase compensation component.
    Type: Application
    Filed: December 20, 2013
    Publication date: October 16, 2014
    Applicant: Spansion LLC
    Inventor: Hideta OKI
  • AUTHENTICATION FOR RECOGNITION SYSTEMS
    Publication number: 20140303983
    Abstract: Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.
    Type: Application
    Filed: April 4, 2013
    Publication date: October 9, 2014
    Applicant: Spansion LLC
    Inventor: Ojas BAPAT
  • COMBINING OF RESULTS FROM MULTIPLE DECODERS
    Publication number: 20140304205
    Abstract: Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders.
    Type: Application
    Filed: April 4, 2013
    Publication date: October 9, 2014
    Applicant: Spansion LLC
    Inventors: Richard FASTOW, Jens OLSON, Chen LIU, Ojas BAPAT
  • MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS
    Publication number: 20140301146
    Abstract: A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 9, 2014
    Applicant: Spansion LLC
    Inventors: Swaroop KAZA, Youseok SUH, Di LI, Sameer HADDAD
  • Table lookup operation on masked data
    Patent number: 8855298
    Abstract: Processing of masked data using table lookups is described. A mask is applied to input data to generate masked input data. The mask and the masked input data are used in combination to locate an entry in a lookup table. The entry corresponds to a transformed version of the input data.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: Spansion LLC
    Inventor: Elena Vasilievna Trichina
  • Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof
    Patent number: 8848452
    Abstract: Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: September 30, 2014
    Assignee: Spansion LLC
    Inventor: Sameer Haddad
  • Device and method for preventing lost synchronization
    Patent number: 8850257
    Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 30, 2014
    Assignee: Spansion LLC
    Inventor: Masato Tomita
  • Inter-Bus Communication Interface Device
    Publication number: 20140289443
    Abstract: There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the buffer to a second device, and passes the communication control information stored in the register to a second device.
    Type: Application
    Filed: June 5, 2014
    Publication date: September 25, 2014
    Applicant: Spansion LLC
    Inventors: Kenichi IIZUKA, Kumiko TOSHIMORI, Machiko MIKAMI
  • Node System and Supervisory Node
    Publication number: 20140286330
    Abstract: A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Applicant: Spansion LLC
    Inventors: Kenji Suina, Takashi ARAI, Koichi MITA, Akira SHIMAMURA, Hidetoshi ISHIKAWA, Takashi MORIYA, Yuuki NOZAWA, Hideki KONDO
  • Method of detecting an operating condition of an electric stepper motor
    Patent number: 8841874
    Abstract: An electrical stepper motor comprises a magnetical rotor and at least two electromagnetical driving coils for causing rotation of the rotator. A method of detecting an operating condition of the as e.g. a stall state of the electrical stepper motor comprises the steps of connecting one contact pin (P, M) of at least one of the electromagnetical driving coils via a high-impedance resistor (R1, R2) to a defined voltage source during a non-activated state of the driving coil, detecting a voltage induced at the driving coil during the non-activated state and converting the detected voltage into a digital signal, and digitally analyzing the digital signal and deriving an operating condition of the rotor by evaluation of the signal waveform including positive and negative components of the signal.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: September 23, 2014
    Assignee: Spansion LLC
    Inventors: Jens Wagner, Armin Dietrich, Kai Dieffenbach, Marco Bodenmüller, Jürgen Rohn, Wolfgang Wiewesiek
  • Method, apparatus, and manufacture for flash memory adaptive algorithm
    Patent number: 8842477
    Abstract: A method, apparatus, and manufacture for a memory device is provided. The memory device includes a memory cell region including sectors, where each sector includes memory cells. The memory device further includes a memory controller that is configured to control program operations and erase operations to the memory cells. During erase operations to the memory cells, pre-programming occurs in which each un-programmed memory cell in the sector being erased is programmed by applying at least one programming pulse at a program voltage until a program verify passes. Then, the program voltage is adjusted based on the number of programming pulses applied until the program-verify passed. During subsequent program operations in that sector, programming pulses are applied with the adjusted program voltage.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 23, 2014
    Assignee: Spansion LLC
    Inventor: Allan Parker
  • Method to improve charge trap flash memory core cell performance and reliability
    Patent number: 8835277
    Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventors: Tung-Sheng Chen, Shenqing Fang
  • Spacer design to prevent trapped electrons
    Patent number: 8836012
    Abstract: Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventor: Angela T. Hui
  • Integrated circuits with non-volatile memory and methods for manufacture
    Patent number: 8836006
    Abstract: Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventors: Kuo Tung Chang, Chun Chen, Shenqing Fang
  • Pipelining in a Memory
    Publication number: 20140254288
    Abstract: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: Spansion LLC
    Inventors: Michael ACHTER, Evrim BINBOGA, Marufa KANIZ, Murni MOHD-SALLEH