Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.

Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Abstract: A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.

Abstract: A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.

Abstract: A method of writing data into a memory device discloses utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank. The method further comprises searching for a data word that is awaiting write verification in the error buffer, wherein the verify operation occurs in a same row as the write operation. The method also comprises determining if an address of the data word is proximal to an address for the write operation and responsive to a positive determination, delaying a start of the verify operation so that a rising edge of the verify operation occurs a predetermined delay after a rising edge of the write operation.

Abstract: Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device; and a third terminal coupled to the first device; wherein at least two terminals in the set of terminals are independent. The third terminal can be coupled to the second device.

Abstract: A magnet mounting apparatus including a cage, a magnet carriage and first actuator for use in testing Magnetic Tunnel Junction (MTJ) devices. The cage can be configured for mounting to an Automated Test Equipment (ATE). The magnet carriage can be configured for coupling to a wafer test magnet. The first actuator can be coupled between the cage and the magnet carriage. The first actuator can be configured to move the magnet carriage between a first position and a second position along a z-axis. The first position can be configured for locating the wafer test magnet within a predetermined proximity to a Device Under Test (DUT) wafer, and the second position can be configured for replacing a probe card.

Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.

Abstract: An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a semiconductor device comprises: a first pillar magnetic tunnel junction (pMTJ) memory cell that comprises a first pMTJ located in a first level in the semiconductor device; and a second pillar magnetic tunnel junction (pMTJ) memory cell that comprises a second pMTJ located in a second level in the semiconductor device, wherein the second pMTJ location with respect to the first pMTJ is coordinated to comply with a reference pitch for the memory cell. A reference pitch is associated a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The first switch and second switch can be transistors. The reference pitch coordination facilitates reduced pitch between memory cells and increased information storage capacity of bits per memory device area.

Abstract: Semiconductor substrate adaptor configured to adapt a substrate of a first dimension to a second dimension, such that the substrate can be properly supported by a supporting mechanism (e.g., a wafer cassette) customized for substrates of the second dimension. The substrate adaptor may be made of quartz. The combination of the substrate adaptor and a substrate fitting therein causes no perturbation in various aspects of a semiconductor process. Therefore, the substrate adaptor conveniently enables a substrate of the first dimension to be processed in the same processing equipment and conditions as a substrate of the second dimension. A vertical substrate adaptor may have a semicircular body with a semicircular cutout for accommodating a wafer and can support a wafer vertically. A horizontal substrate adaptor may have a circular body with a circular cutout for accommodating an entire wafer and supporting the wafer horizontally.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, the method comprises: forming a first pitch reference component and a second pitch reference component; forming a first pillar magnetic tunnel junction (pMTJ) located in a first level and a second pMTJ located in a second level, wherein the location of the second pMTJ with respect to the first pMTJ is coordinated based upon a reference pitch distance between the first pitch reference component and first pitch reference component. In one exemplary implementation, the first pitch reference component is a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The reference component size can be based upon a minimum lithographic processing dimension.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a free magnetic layer having a predetermined smoothness. An etching process for smoothing the free magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Abstract: A memory device comprises a memory bank comprising a plurality of memory addresses. The memory device further comprises a first level dynamic redundancy register comprising data storage elements and a pipeline bank coupled to the memory bank and the first level dynamic redundancy register, wherein the pipeline bank is configured to: (a) write a data word into the memory bank at a selected one of the plurality of memory addresses; (b) verify the data word written into the memory bank to determine whether the data word was successfully written by the write; and (c) responsive to a determination that the data word was not successfully written by the write, writing the data word into the first level dynamic redundancy register, wherein the memory bank is fabricated on a first die and further wherein the first level dynamic redundancy register is fabricated on a second die.

Abstract: A method for fabricating an array of pillars. The method includes fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer. The method selects between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer. For electron beam patterning, an electron beam lithography hard mask is deposited onto the metal stack, and an electron beam is used to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array. For photolithography patterning, a photolithography hard mask is deposited onto the metal stack, and photolithography is used to pattern a second array of pillars into the photolithography hard mask to produce a second resulting pillar array. The first resulting pillar array is substantially the same as the second resulting pillar array.

Abstract: A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Re) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.

Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.