Abstract: A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second precessional spin current ferromagnetic layer separated by a nonmagnetic precessional spin current insertion layer.

Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.

Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: A magnetic field transducer mounting apparatus can include a first mount configured to fixedly couple to a side surface of a wafer test fixture magnet, and a second and third mount configured to adjustably position a magnetic field transducer in a predetermined location proximate a face of the wafer test fixture magnet.

Abstract: A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed by biasing a selected word line, a selected bit line, and a selected source line coupled to corresponding column of memory cells coupled to the selected bit line, and by counter biasing one or more selected source lines coupled to one or more other columns of memory cells coupled to the selected bit line.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second precessional spin current ferromagnetic layer separated by a nonmagnetic precessional spin current insertion layer.

Abstract: A system for a nonvolatile memory for broad temperature range applications. The system includes a memory organized into an addressable memory range and comprising a plurality of memory arrays comprising memory cells wherein each memory array is configured for operation over a different temperature range, and a buffer for receiving a data word and an associated address for writing into the memory. A temperature sensor is used for sensing a current temperature of operation of the memory. A write controller is coupled to the buffer, the temperature sensor and the memory. The write controller is operable to perform a write operation that includes accessing a temperature value from the temperature sensor, selecting a selected memory array of the plurality of memory arrays that is configured for operation at the temperature value, and writing the data word, at the associated address, to the selected memory array.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.

Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a spin current injection capping layer between the free layer of a magnetic tunnel junction and the orthogonal polarizer layer. The spin current injection capping layer maximizes the spin torque through very efficient spin current injection from the polarizer. The spin current injection capping layer can be comprised of a layer of MgO and a layer of a ferromagnetic material.

Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM bit cell consists of a magnetic tunnel junction stack having a significantly improved performance of the magnetic storage layer. The MRAM device utilizes a polarizer layer with a magnetic vector that can switch between a stabilizing magnetic direction and a programming magnetic direction.

Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate.

Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.

Abstract: A memory device includes a write port, a read port, source lines, bit lines, and word lines orthogonal to the bit lines. The memory device also includes memory cells that can be arrayed in columns that are parallel to the bit lines and in rows that are orthogonal to the bit lines. The memory cells are configured so that a write by the write port to a first memory cell in a column associated with (e.g., parallel to) a first bit line and a read by the read port of a second memory cell in a column associated with (e.g., parallel to) a second, different bit line can be performed during overlapping time periods (e.g., at a same time or during a same clock cycle).