Abstract: Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve.

Abstract: A computer-implemented method to debug testbench and the associated circuit design by recording a trace of call frames along with the activities of the circuit design. By correlating and displaying the recorded call frames, the method enables users to easily trace the execution history of the subroutines and debug the testbench code. In addition, users can trace the source code of the testbench by using the trace of call frames. Furthermore, users can debug with a virtual simulation, which is done by post-processing the simulation records stored in a database.

Abstract: A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

Abstract: A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources.

Abstract: A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

Abstract: A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns.

Abstract: A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit.

Abstract: A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources.

Abstract: To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

Abstract: A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

Abstract: A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) representation of a trial placement wherein each symmetry group and each module not included in a symmetry group is represented by a separate node of the HB*-tree. Each symmetry group node maps to a symmetry island placement for the symmetry group satisfying all symmetry and other placement constraints on the symmetry group. The placement tool employs a simulated annealing technique to iteratively perturb the HB*-tree representation to produce a sequence of trial placements, and uses a cost function to evaluate the quality of each trial placement.

Abstract: A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC.

Abstract: An integrated circuit (IC) tester tests an IC having logic blocks that communicate through clocked devices arranged into scan chains. The tester organizes a low-speed IC functional test into a succession of test cycles, each of a uniform test cycle period, and can clock each clocked device up to once per test cycle with adjustable clock signal edge timing. At selected times during the functional test, the tester executes a capture procedure wherein it adjusts clock signal edge timing so that a delay between clocking of the input and output signals of selected logic blocks is less than the test cycle period to determine whether those logic blocks can operate at high frequency without delay faults. The tester executes a scan procedure immediately following each capture procedure to acquire data representing states of logic block output signals to enable the tester to determine whether one or more selected logic blocks experienced delay faults during the capture procedure.

Abstract: A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and specifying a constraint on relative placement within the schematic diagram of symbols representing devices forming the pattern. The generator identifies each set of devices in the netlist that exhibits any rule's interconnection pattern as a separate “soft group”, places a constraint consistent with the rule on relative positioning within the schematic diagram of symbols representing the soft group, resolves any constraint conflicts in accordance with a constraint resolution scheme, and then places all device symbols in the schematic diagram in a manner consistent accordance with the constraints.

Abstract: A co-verification system includes a computer programmed to act as a simulator for simulating behavior of a first portion of an electronic device under test (DUT) by acquiring, processing and generating data representing DUT signals. The co-verification system also includes emulation resources programmed to emulate a second portion of the DUT by receiving, processing and generating emulation signals representing DUT signals. The signals of the DUT are mapped to separate addresses within a memory space, and the simulator controls and reads states of emulation signals by writing data to and reading data from addresses of the memory space states mapped to the DUT signals the emulation signals represent. The computer and the emulation resources are also programmed to implement transactors communicating with one another through a packet routing network. The transactors set states of the emulation signals when the simulator writes to memory space addresses and for reading states of the emulation signals.

Abstract: A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns.

Abstract: An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding electronic device, and the shape and position of each object within the cell layout represents the shape and position of the corresponding portion of IC material within the corresponding electronic device. When a dimension or position of an object within a cell's internal layout can be altered without affecting the behavior of the electronic device the cell describes, a device rule is created for that cell to indicate any constraint on that object's dimension or relative position. The IC layout is then compacted both by moving cell instances closer together, and also by altering internal layouts of cell instances in a manner consistent with their device rules.

Abstract: A routing tool allows a user to create a set of routing templates, each specifying the shape of a routing corridor and identifying the corridor's terminal edges. Each routing template also specifies a set of constraints on routing of an unspecified number of conductors that are to be routed between the corridor's terminal edges. To direct the tool to create a routing plan for a particular set of conductors in a particular routing space, the user selects one of the routing templates and modifies the routing template if necessary to adjust the specified shape of the corridor to match that of the particular routing space or to adjust its specified routing constraints if necessary to accommodate any particular routing constraints to be imposed on that set of conductors. The routing tool then processes the modified routing template to generate the routing plan for routing the set of conductors between the terminal edges of the specified corridor in a manner that satisfies the specified routing constraints.

Abstract: While simulating a circuit described by the netlist, a circuit simulator produces a dump file containing a set of waveform data sequences, each corresponding to a separate signal within the circuit, and representing states of its corresponding signal at a succession of times during the circuit simulation. Based on a mapping of the waveform data sequences to lines of a bus, and on transaction data models describing characteristic signal patterns appearing on the bus during each type of transaction that can occur on the bus, a transaction analysis system identifies transactions that occurred on the bus during the simulation. The transaction analysis system also notes a time during the circuit simulation in which each transaction occurred, and generates a display including a separate representation of each identified transaction positioned to represent the time the transaction occurred.

Abstract: A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnected instances of a device unit, such as a resistor segment or a capacitor block. User-supplied Input parameter values control the number of instances of the device unit included in the passive device layout, the relative positions of the device unit instances, and characteristics of their internal layouts. The tool also generates a display of a representation of the passive device layout and provides a graphical interface enabling the user to modify various aspects of the passive device layout by altering its displayed representation.