Abstract: A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations of the nets. When a user requests a zoom in operation to display a smaller portion of the schematic diagram at a scale at which net representations can be viewed, the system determines routes for representations of nets that are to reside in that portion of the schematic diagram and then displays those net representations upon zooming in to that portion of the schematic diagram.

Abstract: A computer-aided design tool for automatically generating a layout for an electronic device to be formed by a set of objects implemented within an integrated circuit, receives input from a user defining a device template specifying shapes, dimensions and relative positions within the layout of the objects forming the device. Some of the object dimensions and/or relative positions are specified as functions of values of input parameters to be supplied by the user. When the user supplies the input parameters, the CAD tool evaluates the functions to determine the object dimensions and/or positions that are functions of the input parameters and then generates a layout for the electronic device wherein object shapes, dimensions and relative positions are as specified in the device template and consistent with the function evaluations.

Abstract: A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs from a desired value. An error set of the error variable is obtained, which is a subset of the statements in the computer readable code. Each statement in the error set is relationally connected to the error variable. A priority value is given to each statement in the error set. The priority values indicate a computed probability that the associated statement is an error source of the error variable. Finally, the output system is used to present each statement in the error set in an ordered manner according to the priority values.

Abstract: A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode.

Abstract: In a computer-implemented method and system for creating a test component layout, after creating a reference component layout that is composed of a set of polygonal working shapes, a plurality of shape parameters are defined for the working shapes of the reference component layout, and a parameter template is formed based on the shape parameters of the reference component layout. Thereafter, user-defined distance values corresponding to the shape parameters may be inputted into the parameter template, and the test component layout is automatically created by adjusting geometry of the working shapes of the reference component layout with reference to the user-defined distance values inputted into the parameter template.

Abstract: Waveform data contains waveform signals having transition events and is subdivided into data blocks. Indexing elements are provided for each waveform signal that correspond to a time range of the waveform data, and have a pointer to a data block within which transition events for the waveform signal are stored. Each indexing element has a maximum interval value that indicates the maximum amount of time spanned between transition events of the waveform signal. A minimum time resolution that may be adequately resolved on the display is computed. For indexing elements having maximum interval values that exceed the minimum time resolution, the pointers of the indexing elements are used to access and draw transition events for the waveform signals. For indexing elements having maximum interval values that are less than the minimum time resolution, a predetermined image in place of transition events for the waveform signals is drawn.

Abstract: HDL code is used to describe a circuit in an HDL code debugger on a computer system. Circuit simulation data is obtained for the circuit, the simulation data being generated according to the HDL code. A circuit execution time is selected, and the simulation data should at least span the circuit execution time. A debugging element is selected, which is a circuit element in the circuit having a debugging state at the circuit execution time according to the simulation data. A target line of HDL code is then presented to a user. The target line of HDL code is the line of code responsible for setting the debugging element into the debugging state at the circuit execution time.

Abstract: Hardware description language (HDL)-centered design system and methodology uses HDL specification effectively as master depository for design intent or knowledge. Through network browser, designers conveniently navigate or explore design graphically. Designers selectively review or save design in entirety or portions. Design capture, analysis, and manipulation are based on HDL specification, either directly through text file editing, or indirectly through use of graphical tools.

Abstract: Prior simulation results and model changes are used to shorten re-simulation time in improved design verification methodology, wherein simulator is re-run on design revision. Accelerated incremental simulation scheme boosts engineer design and verification productivity, and facilitates storage of different design revisions and simulation results.