Simulcast standard multichip memory addressing system

Abstract

The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.

Claims

1. A memory addressing subsystem for an electronic data processing system of the type including a system bus to communicate a variety of signals between system elements and system memory, said memory addressing subsystem comprising:

a) a memory address register and refresh counter coupled to the system bus for receiving a multiple bit memory address via the system bus, and providing a multiple-bit address output signal in parallel format;

b) a timing and control circuit coupled to the system bus to receive system memory access timing and control input signals and for providing row address strobe, column address strobe and refresh timing and control output signals;

c) an address multiplex circuit coupled to said memory address register to receive said multiple-bit address signal and to provide a multiplexed multiple-bit address output signal in parallel format comprising a row address followed by column address;

d) a memory module level decode circuit, said level decode circuit being coupled to said memory address register for receiving a multiple-bit encoded level select input signal; said level decode circuit also being coupled to said timing and control circuit to receive said row address strobe and refresh control signals as inputs; said level decode circuit providing a multiple-bit memory module level select output signal in response to said inputs;

e) a memory module socket adapted to receive memory modules comprised of either single level memory devices or high-density, multiple-level memory devices;

f) wherein said single level memory devices are coupled to receive said row and column address strobe signals from said timing and control circuit and to receive said multiplexed multiple-bit address output signal from said address multiplex circuit; and

g) wherein said high-density, multiple level memory devices are coupled to receive; said column address strobe signal from said timing and control circuit; said multiple-bit memory module level select output signal; and to receive said multiplexed multiple-bit address output signal from said address multiplex circuit.

2. The memory address subsystem of claim 1, wherein said multiple-bit memory module level select output signal provided by said memory module level decode circuit comprises a decoded output level select signal or a multiple output level select signal in the case of a refresh cycle.

3. The memory address subsystem of claim 2, wherein said multiple-bit encoded level select input signal to said memory module level decode circuit comprises the least significant bits of the multiple-bit address output signal from said memory address register.

4. The memory address subsystem of claim 2, wherein said multiple-bit encoded level select input signal to said memory module level decode circuit comprises the most significant bits of the multiple-bit address output signal from said memory address register.

5. The method of addressing system memory, comprising a plurality of memory devices in a multi-level configuration in a computer system of the type including a system bus, a data processor, a system memory interface circuit, a means for generating memory address signals, and a means for generating memory timing and control signals, said system memory addressing method comprising:

a) providing conventional row and column address strobe signals to said system memory;

b) providing multiple-bit address signals to said system memory, said address signals including conventional row and column address specifying bits and also including memory module level select bits;

c) providing a level select signal to said system memory in response to decoding of said memory module level select bits; said level select signal being utilized to select one of said plurality of multi-level commonly coupled memory devices comprising said system memory for access; and

d) providing multiple-bit refresh address signals to said system memory, said address signals including conventional refresh row address bits and also including said memory module level select bits..Iadd.

6. A memory addressing subsystem for an electronic data processing system of the type including a system bus to communicate a variety of signals between system elements and system memory, said memory addressing subsystem comprising:

a) a memory address register and refresh counter coupled to the system bus for receiving a multiple-bit memory address via the system bus, and providing a multiple-bit address output signal expressing a memory address;

b) a timing and control circuit coupled to the system bus to receive system memory access timing and control input signals and for providing row address strobe, column address strobe and refresh timing and control output signals;

c) an address multiplex circuit coupled to said memory address register to receive said multiple-bit address output signal and to provide a multiplexed multiple-bit address output signal expressing said memory address;

d) a memory module decode circuit, said decode circuit arranged to receive an encoded select input signal derived from said memory address; said decode circuit also being coupled to said timing and control circuit to receive said row address strobe said refresh timing and control signals as inputs; said decode circuit providing a multiple-bit memory module select output signal in response to said inputs;

e) a memory module socket adapted to receive a memory module and provide said memory module with said multiple-bit memory module select output signal and an address signal set derived from said multiplexed multiple-bit address output signal..Iaddend..Iadd.

7. A memory unit selection system for a computer, said system comprising:

a defined memory space having a set of memory addresses;

plural memory units designated within said defined memory space;

memory interface circuitry for generating a multi-bit memory address signal within the set of memory addresses;

a row address strobe generator producing a row address strobe signal in substantial correspondence with a computer access of said defined memory space;

a decode circuit responsive to said row address strobe signal to produce one of a set of plural row address unit select strobe output signals to select an individual one of said plural memory units in correspondence with the information content of a unit select signal derived from said multi-bit memory address signal..Iaddend..Iadd.

8. A method for selecting a memory unit within a defined memory space associated with a computer system, said method comprising the steps of:

providing a defined memory space having a set of memory addresses;

designating plural memory units within said defined memory space;

generating a multi-bit memory address signal within said set of memory addresses;

deriving a unit select signal set from said multi-bit memory address signal;

generating a row address strobe signal in substantial correspondence with a computer system access of said defined memory space;

providing a decode circuit having plural row address select strobe signals;

conveying said unit select signal set and said row address strobe signal to said decode circuit to generate, at a state change of said row address strobe signal, a selected row address select strobe signal corresponding to a selected memory unit as determined by the information content of said unit select signal set..Iaddend..Iadd.

9. The method of claim 8 wherein said unit select signal set is derived by the decode circuit from said multi-bit memory address signal by decoding the combination of a signifying row address datum and a signifying column address datum received from said multi-bit address memory signal..Iaddend..Iadd.10. The method of claims 8 or 9 wherein N memory units are designated within said defined memory space and said unit select signal set has X number of bits where: