Patents Assigned to STAT ChipPAC, Ltd.
  • Patent number: 8810015
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: August 19, 2014
    Assignee: STAT ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Dahilig
  • Patent number: 8772916
    Abstract: An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Patent number: 8766428
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other; connecting a first circuit device between the tips; attaching a second circuit device to the first circuit device with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and forming an encapsulation of the first thickness between the bases and over the tips.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: July 1, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
  • Patent number: 8759159
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: June 24, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8748233
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: June 10, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, Oh Han Kim, Jung Sell
  • Patent number: 8735224
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: May 27, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Zigmund Ramirez Camacho
  • Patent number: 8729693
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 20, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Patent number: 8723302
    Abstract: An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: May 13, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Harry Chandra, Flynn Carson
  • Patent number: 8723324
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 13, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8723310
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 13, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: YiSu Park, KyungHoon Lee, Joungln Yang, SangMi Park, DaeSik Choi
  • Patent number: 8723338
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: May 13, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Patent number: 8716065
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 6, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 8716108
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, DaeWook Yang, Yeongbeom Ko
  • Patent number: 8709877
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an integrated circuit device having a device contact surface, a device lateral side, and a device backside opposite the device contact surface; forming a device shell, having a shell lip, contiguous with the device backside and the device lateral side, the shell lip adjacent to and coplanar with the device contact surface; attaching a substrate to the integrated circuit device, the device shell between the integrated circuit device and the substrate; and forming an encapsulation on the substrate and covering the integrated circuit device and the device shell.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: April 29, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DaeWook Yang, Yeongbeom Ko
  • Patent number: 8710634
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an integrated circuit above and to the substrate; mounting an internal interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate and over the integrated circuit with the integral-interposer-structure connected to the internal interconnect; and encapsulating the internal interconnect and the integrated circuit with an encapsulation.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: April 29, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: HeeJo Chi, Jae Han Chung, Junwoo Myung, Yeonglm Park, HyungMin Lee
  • Patent number: 8709932
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: April 29, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Soo Won Lee, JiHoon Oh, Sung Jun Yoon
  • Patent number: 8709873
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 29, 2014
    Assignee: Stats ChipPac Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 8709934
    Abstract: An electronic system is provided including forming a substrate having a contact, forming a conductive structure over the contact, mounting an electrical device having an external interconnect over the conductive structure, and forming a conductive protrusion from the conductive structure in the external interconnect.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: April 29, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: BaeYong Kim, Bongsuk Choi, Oh Han Kim
  • Patent number: 8710668
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; molding a first encapsulation above the substrate; forming a via through the first encapsulation; mounting an integrated circuit above the substrate and between sides of the first encapsulation; and forming a second encapsulation covering the integrated circuit and the first encapsulation.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: April 29, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: HyungMin Lee, HeeJo Chi, YeongIm Park
  • Patent number: 8710675
    Abstract: An integrated circuit package system includes a first integrated circuit die having die pads only adjacent a single edge of the first integrated circuit die, forming first bonding lands adjacent the single edge, connecting the die pads and the first bonding lands, and encapsulating the die pads and a portion of the first bonding lands to form a first package.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 29, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Young Cheol Kim, Koo Hong Lee