Patents Assigned to STAT ChipPAC, Ltd.
  • Patent number: 8643166
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8642382
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a mountable assembly includes: forming an integrated circuit device having a non-horizontal device side, an active device side, and a passive device side, providing a first integrated circuit die having an active side, a passive side, and an internal interconnect on the active side, applying a die attach adhesive on the passive side, attaching the passive side to the passive device side with the die attach adhesive, and applying an underfill on the passive device side and the internal interconnect, the underfill having a non-horizontal underfill side coplanar with the non-horizontal device side; and mounting on a substrate the mountable assembly.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Reza Argenty Pagaila, Rui Huang
  • Patent number: 8643157
    Abstract: An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the active side facing the paddle and the hole; connecting a first internal interconnect between the active side and the external interconnect through the hole; and encapsulating the integrated circuit device, the paddle, the first internal interconnect, and the external interconnect with the external interconnect partially exposed.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 8633058
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, Jong-Woo Ha, Seung Won Kim
  • Patent number: 8633578
    Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8632112
    Abstract: A method of operation of a workpiece displacement system includes: providing a head including a conduit, a recess port, and a channel, the conduit configured such that its major axis intersects the recess port and the channel; inserting a force distribution member into the recess port; and supplying a negative pressure state through the head and the force distribution member.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hyunjoo Kim, Hunki Lee, Changyong Lee, Jong Wook Ju, Sang-Ho Lee
  • Patent number: 8633059
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; providing a first integrated circuit having a first integrated circuit inactive side and a first integrated circuit active side; coupling a second integrated circuit, having a second integrated circuit inactive side and a second integrated circuit active side, to the first integrated circuit in an active-to-active configuration; attaching the first integrated circuit over the base carrier; attaching a redistribution structure over the first integrated circuit; and forming a base encapsulation over the redistribution structure, the base encapsulation having a recess partially exposing the redistribution structure.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Reza Argenty Pagaila
  • Patent number: 8633586
    Abstract: A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Oh Han Kim, BaeYong Kim, YoungMin Kim
  • Patent number: 8633100
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a connection post on the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; molding an encapsulation on the integrated circuit die and the connection post; and forming a connector recess in the encapsulation by removing the encapsulation around the connection post exposing a portion of the post side.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, In Sang Yoon, SangJin Lee
  • Patent number: 8633062
    Abstract: A method of manufacture of an integrated circuit package system includes: forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descaizo Bathan, Zigmund Ramirez Camacho, Amel Trasporto
  • Patent number: 8633056
    Abstract: A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hyung Jun Jeon, Tae Keun Lee, Sung Soo Kim
  • Patent number: 8633063
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8629567
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8629537
    Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8623708
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a lead-frame having an inner portion and a bottom cover directly on a bottom surface of the inner portion; forming an insulation cover directly on the lead-frame with the insulation cover having a connection opening; connecting an integrated circuit die to the lead-frame through the connection opening with the integrated circuit die over the insulation cover; forming a top encapsulation directly on the insulation cover; forming a routing layer having a conductive land directly on the bottom cover by shaping the lead-frame; and forming a bottom encapsulation directly on the conductive land with the bottom cover exposed from the bottom encapsulation.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8624370
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: HeeJo Chi, NamJu Cho, Taewoo Lee
  • Patent number: 8624364
    Abstract: An integrated circuit packaging system includes: a base integrated circuit package having a base integrated circuit on a base substrate thereof; a base barrier on the base substrate adjacent a base perimeter of the base substrate; a stack substrate over the base substrate, the stack substrate having a stack substrate aperture with the stack substrate having an inter-substrate connector thereon; a connector underfill through the stack substrate aperture encapsulating the inter-substrate connector, overflow of the connector underfill prevented by the base barrier; and a cavity formed of the stack substrate, the base integrated circuit package, and the connector underfill, the cavity horizontally offset from the base barrier.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Hin Hwa Goh, Rui Huang, Heap Hoe Kuan
  • Patent number: 8623711
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 7, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8617933
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8617924
    Abstract: A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: OhSug Kim, Jong-Woo Ha, Jong Wook Ju