Patents Assigned to STAT ChipPAC, Ltd.
  • Patent number: 8709873
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 29, 2014
    Assignee: Stats ChipPac Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 8703535
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: MinJung Kim, DaeSik Choi, MinWook Yu, YiSu Park
  • Patent number: 8704349
    Abstract: An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions of the interconnects exposed; attaching solder balls to the second surface; and singulating the substrate and the encapsulant into a plurality of integrated circuit packages.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: April 22, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, II Kwon Shim, Byung Joon Han
  • Patent number: 8703538
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Stats Chippac Ltd.
    Inventor: DaeSik Choi
  • Patent number: 8703541
    Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 22, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Haengcheol Choi, Ki Youn Jang, Taewoo Kang, Il Kwon Shim
  • Patent number: 8699232
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, DeokKyung Yang, JoHyun Bae
  • Patent number: 8692377
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: April 8, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8692365
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: April 8, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DongSoo Moon, Taewoo Lee, Soo-San Park, SooMoon Park, Sang-Ho Lee
  • Patent number: 8692388
    Abstract: An integrated circuit packaging system is provided including: a first device having a first backside and a first active side; and a waferscale spacer having an exact fit at all four corners adjacent to an edge of the first device and a recess along the edge of the first device.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 8, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Sang-Ho Lee, Jong-Woo Ha, Soo-San Park
  • Patent number: 8685792
    Abstract: An integrated circuit package system includes: providing a mountable integrated circuit system having an encapsulation with a cavity therein and a first interposer exposed by the cavity; mounting a second interposer over the first interposer for only stacking a discrete device thereover, and with the second interposer over the encapsulation and the cavity; and mounting an electrical component over the second interposer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: April 1, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Il Kwon Shim
  • Patent number: 8685797
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: April 1, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Soo-San Park, Sang-Ho Lee, DaeSik Choi
  • Patent number: 8679900
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; mounting a lid base over the substrate, the lid base having a base indentation and a hole with the integrated circuit within the hole; and mounting a heat slug over the lid base, the heat slug having a slug non-horizontal side partially within the base indentation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, SangMi Park, MinJung Kim, MinWook Yu
  • Patent number: 8674516
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Joon Han, In Sang Yoon, JoHyun Bae
  • Patent number: 8669649
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a lead overhang protruding from a lead non-horizontal side and a lead ridge protruding from the lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming an encapsulation over the integrated circuit, the lead, and the package paddle, the encapsulation under the lead overhang.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 11, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8669637
    Abstract: An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: March 11, 2014
    Assignee: Stats ChipPac Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Robert Charles Frye, Pandi Chelvam Marimuthu
  • Patent number: 8664038
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle and a terminal adjacent to the package paddle; mounting a stack paddle over the package paddle with the stack paddle at a non-center offset with the package paddle; mounting a stack integrated circuit over the stack paddle; and encapsulating the stack integrated circuit and the stack paddle.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 8659175
    Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
  • Patent number: 8658470
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; attaching an integrated circuit device on the die paddle, the trench between the integrated circuit device and the perimeter; attaching an electrical connector to the integrated circuit device and to the upper portion; and applying an encapsulation over the integrated circuit device, the electrical connector, the die paddle, and the interconnect, the concave indentation exposed below the encapsulation.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: February 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8653654
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base assembly having a cavity and a through conductor adjacent to the cavity; connecting a first device to the base assembly with the first device within the cavity; connecting a second device to the base assembly with the second device within the cavity; and connecting an interposer substrate having an exposed external side over the through conductor with the exposed external side facing away from the through conductor and exposed to ambient.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: February 18, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Harry Chandra, Robert J. Martin, III
  • Patent number: 8642383
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a first lead-finger system and a second lead-finger system; connecting a first device to the first lead-finger system with a wire bond; stacking a second device over the first device; and connecting the second device to the second lead-finger system with a bump bond.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, BumJoon Hong