Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved.

Abstract: A signal processor for processing a digital input signal including samples sampled at a sampling frequency, the signal processor comprising a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency; first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency; decimation circuitry arranged to decimate the first signal and the shifted second signal; and processing circuitry arranged to process the decimated first and second signals.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to the state machine to the devices relating to scan testing. The state machine supports a plurality of data transfer protocols. The choice of the protocol to be used is made as a function of a signal received on the input pin. Responsive to an input pin signal, the state machine enters an operational mode wherein scan test programming data is serially received at the input pin and communicated to the devices which facilitate scan testing. More specifically, the scan test programming data is serially communicated to a scan test register, where the data is output in parallel to the scan test device.

Abstract: An integrated circuit includes at least one interconnection level and an acoustic resonator provided with an active element and a support. The includes at least one bilayer assembly having a layer of high acoustic impedance material and a layer of low acoustic impedance material. The support further includes a protruding element arranged on a metallization level of the interconnection level, making it possible to produce an electrical contact between an interconnection level and the active element of the acoustic resonator.

Abstract: External electrical connection pads are provided on a semiconductor device. A well is formed in an outer surface for the semiconductor device to at least partially expose an internal electrical connection pad. An electrical connection tab is formed which has an internal branch extending over the internal pad, an external branch extending over a top of the outer surface and extending from one side edge of the well, and a linking branch extending over a sidewall of the wells between the external branch and the internal branch.

Abstract: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improves the overall dielectric constant of the resulting dielectric element.

Abstract: A method and a circuit for detecting a possible loss of the equiprobable character of a first output bit flow originating from at least one first normalization element of an initial bit flow, consisting of submitting the initial flow to at least one second normalization element of a nature different from the first one, pairing, bit to bit, the flows originating from the two elements, and checking the equidistribution of the different state pairs.

Abstract: A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly second copper silicide molecules. The proportion of the number of silicon atoms is higher in the second silicide molecules than in the first silicide molecules. The second copper silicide layer is positioned between the copper portion and the first copper silicide layer. A nitride layer may overlie at least part of the first copper silicide layer.

Abstract: A method for reading of the state of a non-volatile memory element including conditioning the frequency of a first oscillator to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element.

Abstract: The invention relates to a method for the COFDM demodulation of a signal received from a transmission channel. The inventive method includes performing the fast Fourier transform of the signal received in a window corresponding to a symbol, each symbol being associated with a guard time reproducing one part of the symbol; supplying a set of estimated values for the module impulse response; determining coefficients, each coefficient being obtained from the product of the aforementioned set and a filtering function (FE) for a determined relative position of the filtering function in relation to the set; determining the maximum coefficient and the corresponding relative position; and positioning the window as a function of the relative position, the filtering function including a central part (LMAX) which has a constant amplitude and a duration equal to the duration of the guard time and which is surrounded by non-zero decreasing edges.

Abstract: A window comparator of an A.C. input voltage, including, between two terminals of application of a voltage representative of the voltage to be measured, two first transistors of a first type, each first transistor being assembled as a current mirror on the second transistor having a first conduction terminal connected to one of the application terminals, the two second transistors having a second common conduction terminal; and two third transistors of a second type assembled as a current mirror between the common conduction terminal of the second transistors and a current source, a D.C. voltage being applied on a first terminal of the current source and an output signal being provided by a second terminal of the current source.

Abstract: An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.

Abstract: An HF control bi-directional switch component of the type having its gate referenced to the rear surface formed in the front surface of a peripheral well of the component, including two independent gate regions intended to be respectively connected to terminals of a transformer having a midpoint connected to the rear surface terminal of the component.

Abstract: A method for performing at least one jump in a program executed by a processor, including determining a result over several bits as an indicator that a desired condition has been complied with, the result corresponding to an operation taking into account at least one predetermined value and at least one current value; and calculating a jump address which is a function of the result.

Abstract: A method of COFDM demodulation of successive symbols, each symbol comprising data carriers and pilots. The method includes, for each symbol, the determination of estimates of the transfer function of the channel for the symbol carriers, including the steps of determining, for first carriers such that, for the frequency positions of the considered carriers, symbols different from the symbol include pilots, a first estimate based on second estimates obtained for pilots having the frequency of the carrier; and determining, for second carriers, a third estimate based on the first estimates. For at least one first carrier, the first estimate is further determined based on at least the third estimate determined for a carrier of a symbol received before the symbol at the same frequency as the carrier.

Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.

Abstract: An integrated circuit includes a substrate and a resistor. The resistor is formed from at least two access wells of a first conductivity type and a deep buried layer electrically connecting the wells. The deep buried layer is at least partly covered by a region of opposite conductivity.

Abstract: A reconfigurable power amplifier includes at least one amplification circuit (E1, E2), and a circuit (6) for controlling the amplification circuit so as to adapt its operation according to an applied input signal (RFin). The circuit for controlling includes a circuit (4, 5) for modifying the compression point of the amplification circuit and for adapting the gain of the amplification circuit in such a manner as to increase the power added efficiency of the circuit for the modified compression point.