Patents Assigned to STMicroelectronic S.A.
  • DESIGN METHOD FOR A DMA-COMPATIBLE PERIPHERAL
    Publication number: 20110022738
    Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.
    Type: Application
    Filed: June 17, 2010
    Publication date: January 27, 2011
    Applicant: STMicroelectronics S.A.
    Inventor: André Roger
  • Antenna having a dielectric structure for a simplified fabrication process
    Patent number: 7876283
    Abstract: An antenna is formed with a self-supporting structure (1), a dielectric structure (2), and a conducting structure (3), each structure being formed from at least one structural element (10; 21, 22; 31-34). The structural elements of the different structures (1, 2, 3) constitute a stack in which these elements (10; 21, 22; 31-34) are connected to each other, and the dielectric structure (2) is formed in the stack by nano-imprinting.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: January 25, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Guillaume Bouche, Sébastien Montusclat, Daniel Gloria
  • Method of controlling a matrix screen and corresponding device
    Patent number: 7876290
    Abstract: A device for controlling a matrix screen includes a scanning circuit. The scanning circuit includes a row control block which successively selects each row, and a column control block which, for each selected row, selects or deselects a set of columns of the screen with the aid of column selection or deselection signals. The temporal evolution of each column selection signal and of each column deselection signal includes a first and a second part separated by an intermediate porch. The column control block, for each column of the screen, determines if the corresponding column has to be selected or deselected, determines the value of the capacitance seen by the column termed the column-capacitance, and adjusts temporal evolution characteristics of the selection or deselection signal of at least one column to be selected or deselected as a function of the determined value of its column-capacitance.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: January 25, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Jean-Raphaël Bezal, Eric Cirot
  • Synchronization pulse generator with forced output
    Patent number: 7876141
    Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 25, 2011
    Assignees: STMicroelectronics Inc., STMicroelectronics S.A.
    Inventors: Benoît Lasbouygues, Sylvain Clerc, Alain Artieri, Thomas Zounes, Françoise Jacquet
  • Integrated circuit comprising a photodiode of the floating substrate type and corresponding fabrication process
    Patent number: 7875915
    Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: January 25, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: François Roy, Arnaud Tournier
  • BULK-MODE RESONATOR
    Publication number: 20110012693
    Abstract: A method for forming a resonator including a resonant element, the resonant element being at least partly formed of a body at least partly formed of a first conductive material, the body including open cavities, this method including the steps of measuring the resonator frequency; and at least partially filling said cavities.
    Type: Application
    Filed: June 4, 2010
    Publication date: January 20, 2011
    Applicant: STMicroelectronics S.A.
    Inventors: Fabrice Casset, Cédric Durand
  • SRAM memory cell protected against current or voltage spikes
    Patent number: 7872894
    Abstract: A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: January 18, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Roche, Francois Jacquet
  • Generating an integrated circuit identifier
    Patent number: 7871832
    Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: January 18, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Fabrice Marinet
  • Capacitive array
    Patent number: 7873191
    Abstract: A capacitive array comprising at least two capacitive entities, comprising a substrate layer. The substrate layer comprises a comb comprising at least four substantially identical teeth, and, for each capacitive entity, a set of fingers comprising one or more interlinked fingers. At least two sets of fingers comprise a different number of fingers, each finger being nested between two teeth of the comb and being substantially identical to the other fingers. The fingers of each set of fingers are substantially distributed symmetrically relative to a median axis of the comb. The comb and the fingers are integrated in a single block.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: January 18, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Jérôme Bach
  • CONTROL OF AN ASYNCHRONOUS MOTOR
    Publication number: 20110006721
    Abstract: The invention relates to a device for controlling the speed and the rotation direction of an asynchronous motor (1), comprising a first circuit (7) with two bi-directional switches (T?4, T?5) individually controlled and having first conducting terminals connected to a common terminal (6) for applying a direct potential (Vcc) and having second conducting terminals that can be respectively connected to the first ends (12, 14) of windings (15, 16) of the motor stator, and a second circuit (3?) with at least two parallel bi-directional switches (T1, T2, T3) individually controlled and having first respective conducting terminals (Ki) connected to the common terminal.
    Type: Application
    Filed: January 4, 2008
    Publication date: January 13, 2011
    Applicant: STMicroelectronics S.A.
    Inventors: Laurent Gonthier, Raynald Achart
  • Integrated circuit tolerant to the locking phenomenon
    Patent number: 7868392
    Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP?, RP?) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN?, RP?) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 11, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Francois Tailliet
  • Lamb wave resonator
    Patent number: 7868517
    Abstract: A Lamb wave resonator includes a piezoelectric layer, and a first electrode against a first face of the piezoelectric layer. The first electrode includes fingers and a contact arm, with each finger including a first side in contact with the contact arm and two other sides parallel to one another. Portions of the piezoelectric layer are at least partially etched between the two fingers to form a recess. The fingers are spaced apart from one another by a distance W calculated according to the following equation: W = n · va lateral f , with ? ? n ? N where, valateral is an acoustic propagation speed of Lamb waves, n is an order of a resonance mode of the Lamb waves, f is a resonance frequency of the Lamb wave resonator.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: January 11, 2011
    Assignees: STMicroelectronics S.A., Centre National de la Recherche Scientifique
    Inventors: Didier Belot, Andreia Cathelin, Alexandre Augusto Shirakawa, Jean-Marie Pham, Pierre Jary, Eric Kerherve
  • Optical semiconductor package having an optical module with a progressively varying refractive index
    Patent number: 7868284
    Abstract: An imaging optical module is designed to be placed in front of an optical image sensor of a semiconductor component. The module includes at least one element which has a refractive index that varies between its optical axis and its periphery, over at least an annular part and/or over its central part. The element may be a tablet in front of the semiconductor sensor or a lens in front of the semiconductor sensor. The direction of variation in refractive index may be oppositely oriented with respect to the table and lens.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 11, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Emmanuelle Vigier-Blanc, Guillaume Cassar
  • Determination of carrier and symbol frequencies in a signal
    Patent number: 7865144
    Abstract: A method and a device for determining, in a signal, a value of the frequency of a carrier and a value of the frequency of symbols carried by the carrier. A band of the signal is analyzed at three points and the relations between the powers at these points enable determining values of the carrier frequency and of the symbol frequency.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: January 4, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Jacques Meyer
  • Light modulating sensing MOSFET transistor and process for manufacturing the same
    Patent number: 7859031
    Abstract: A Light Modulating sensing MOSFET transistor includes: a substrate receiving light radiation, the substrate having two source and drain areas separated by a channel extending along a first direction; a gate conductive beam extending along a second direction being substantially perpendicular to the first direction, the beam being fixed at each of its two opposite ends on at least one supporting area and being located above the channel area, the gate beam being substantially opaque and flexible so as to perform progressive modulation of the light reaching the channel in accordance with its bending controlled by the difference of voltage between the gate and the bulk and causing the beam to bend and to come closer to the surface of the channel. A process for manufacturing a light Modulating sensing MOSFET transistor is also provided.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: December 28, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Nicolas Abelé
  • SOFT OUTPUT VITERBI DECODER ARCHITECTURE
    Publication number: 20100325525
    Abstract: A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 23, 2010
    Applicant: STMicroelectronics S.A.
    Inventor: Vincent Heinrich
  • CHECKING OF THE SKEW CONSTANCY OF A BIT FLOW
    Publication number: 20100325183
    Abstract: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.
    Type: Application
    Filed: August 9, 2010
    Publication date: December 23, 2010
    Applicant: STMicroelectronics S.A.
    Inventors: Pierre-Yvan Liardet, Yannick Teglia
  • VERIFICATION OF DATA READ IN MEMORY
    Publication number: 20100325320
    Abstract: A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element.
    Type: Application
    Filed: October 18, 2008
    Publication date: December 23, 2010
    Applicants: STMicroelectronics S.A., Proton World International N.V.
    Inventors: Fabrice Romain, Jean-Louis Modave
  • Testing of an algorithm executed by an integrated circuit
    Patent number: 7853010
    Abstract: A method for testing the resistance of an algorithm using at least one secret quantity against attacks measuring physical effects of the execution of the algorithm by an integrated circuit, consisting of implementing statistical key search functions based on hypotheses about at least some bits thereof, by exploiting the input and output values of steps of the algorithm.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: December 14, 2010
    Assignee: STMicroelectronics S.A.
    Inventor: Yannick Teglia
  • Electronic component comprising a titanium carbonitride (TiCN) barrier layer and process of making the same
    Patent number: 7851915
    Abstract: An electronic component comprising several superimposed layers of materials including a TiCN barrier layer. A process for depositing a TiCN layer in order to obtain an electronic component, where a titanium precursor is chosen from among tetrakis(dimethylamido)titanium and/or tetrakis(diethylamido)titanium and is decomposed on a substrate by plasma-enhanced atomic layer deposition (PEALD) where the plasma is obtained with a hydrogen-rich gas which can contain nitrogen with at most 5 atomic % nitrogen and at least 95 atomic % hydrogen.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 14, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Pierre Caubet, Rym Benaboud