Abstract: A method for writing in an electrically erasable and programmable non-volatile memory (EEPROM, Flash EEPROM) includes keeping a gate of a selection transistor at its maximum value for the erasure or programming of a memory cell, so long as the potential at a drain or source of the transistor is not zero or at a very low level. This increases the lifetime of the selection transistors.

Abstract: A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RA

Abstract: A process is for controlling a memory-plane refresh of a dynamic random-access memory. After having selected at least one first reference memory cell structurally similar to the memory cells of the memory plane, to store a first predetermined binary information item therein, the voltage across the terminals of the storage capacitor of this first reference memory cell is compared with a first predetermined reference voltage. When the voltage reaches the reference voltage, a control signal is delivered in response to which the memory plane is refreshed, then the first reference memory cell is again selected in order to refresh its contents.

Abstract: An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.

Abstract: The reading circuit comprises a current source, which, via a current reflection circuit, supplies a constant predetermined current to a cell to be read, an operational amplifier with a non-inverting input connected to the drain terminal of the cell, and an output connected to the gate terminal of the cell. The source terminal of the cell is connected to ground. Thereby the output voltage of the operational amplifier supplies directly (at the set current) the threshold voltage of the cell, and the drain terminal of the cell is biased to a positive voltage.

Abstract: An electrically erasable and programmable non-volatile semiconductor memory includes memory registers that are addressable individually or by blocks. The memory also has a protection register in which a protection word can be written. The protection word has a given number of bits that encode a boundary address of the memory register or a block of memory registers. The boundary address divides the memory space into an upper zone and a lower zone. The protection word also has a zone bit whose value determines which of the two zones of the memory is to be write protectable.

Abstract: An antenna coil with low electrical field emissions comprises a flat winding with a specified shape and a conductive screen facing the winding. The conductive screen has substantially the same shape as the winding, and includes a cut-off zone. The screen neutralizes the parasitic electrical field emitted by the winding without disturbing the useful magnetic field which is axially oriented (i.e., oriented perpendicularly to the plane of the coil). Such an antenna coil is applicable to a station for the transmission-reception of data by inductive coupling.

Abstract: A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.

Abstract: A contactless chip card, receiving binary data transmitted by radio frequency, includes a demodulator for the binary data. The demodulator includes a circuit for the detection of the transmitted signals, a rectifier circuit, a bandpass filter, two comparators and a memory circuit. The bandpass filter provides a low-frequency signal used as a reference for the two comparators and a high-frequency signal that is compared with the references varying with the low frequency signal. As a result, the demodulation is independent of the mean level of the received signal.

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance. The circuit avoids the switch-on of parasitic bipolar transistors of the LDMOS structure during transient states. The circuit includes a number of junctions directly biased between a source node and a body node of the LDMOS transistor, a current generator referred to a ground of the circuit, at least one switch between the source and a first junction of a chain of directly biased junctions, and a limiting resistor connected between the body and the current generator referred to ground. The switch is open during a charging phase of the capacitance and is closed when the charging voltage of the capacitance exceeds a preestablished threshold responsive to a control signal.

Abstract: Switching circuit that receives a supply voltage, a reference voltage, a line adapted to carry a negative voltage and a control signal, the switching circuit capable of providing at an output a voltage alternatively equal to the reference voltage or to the voltage of the line in response to the control signal. The circuit includes a first MOSFET with a first electrode operationally connected to the line, a second electrode operationally connected to the output, and a control electrode, a second MOSFET with a first electrode operationally connected to the reference voltage, a second electrode operationally connected to the output, and a control electrode, and driving circuitry adapted to bring the control electrodes of the first and second MOSFETs respectively to the supply voltage and to the voltage of the line or, alternatively, to the voltage of the line and to the supply voltage, in response to the control signal.

Abstract: The method described provides for the formation of an implantation mask of polycrystalline silicon comprising strips for providing the gate electrodes of the MOS transistors and portions defining openings for the formation of resistors. The method further includes low-dose ionic implantation through the implantation mask to form pairs of regions at the sides of the gate strips and resistive regions through the openings, the formation of an insulating layer on the entire structure thus produced, and anisotropic etching of the insulating layer so as to uncover the areas of the substrate not covered by the polycrystalline silicon mask, but leaving a residue of insulating material along the edges of the gate strips.

Abstract: A level shift circuit for a voltage input signal (S, SN) presenting at least a first and a second high-voltage levels, the circuit comprising two parallel branches, each formed by a current modulator and a signal converter. The current modulators are supplied with two signals in phase opposition to each other, and generate current signals whose value depends on the level of the respective input signal; and the signal converters convert the current signals into ground-related voltage signals. The signal converters together form a single-ended differential circuit, the output of which therefore presents a low-voltage digital signal which can be processed by normal digital circuits and is unaffected by noise or variations in supply voltage.

Abstract: The invention relates to a driving circuit for row decoding which is also useful in non-volatile memory devices of the multi-level Flash type and the multi-level EPROM type and allows the overall capacitive loads as seen from the program voltage generator and the read/verify voltage generator, to be drastically reduced without involving segmentation of the decoding circuit.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract: A mixed mode PWM/Linear driving system for at least one inductive-resistive (L-R) actuator as a function of operating conditions thereof includes a first full bridge power stage including four power switching devices arranged in pairs for being driven in phase opposition. The system also includes a pulse width modulation (PWM) converter for producing a PWM signal directly driving the first full bridge power stage during a PWM mode operating phase. A second full bridge power stage also comprises four power switching devices of different electrical characteristics from the power switching devices of the first full bridge power stage. The system further includes a pair of amplifiers connected to respective pairs of power switching devices of the second full bridge power stage for driving same in phase opposition during a linear mode operating phase. A switch is provided for switching between the PWM mode operating phase and the linear mode operating phase.

Abstract: A dual gain amplifier provides separate gains so that the amplifier's input characteristics are unaffected by the gain selected. The dual gain amplifier comprises a first input amplifier and a third amplifier connected in cascade, and a second input amplifier and a fourth amplifier connected in cascade. A first LC circuit is connected in parallel to a second LC circuit which are both connected to the third amplifier. Likewise, a third LC circuit is connected in parallel to a fourth LC circuit which are connected to the fourth amplifier. The first and third LC circuits have a first quality factor and the second and fourth LC circuits have a second quality factor. The dual gain amplifier switches from a first state in which only the first and third LC circuits conduct to a second state in which all four LC circuits conduct.

Abstract: The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the drain and the source are connected to a current source adapted to bias the drain and source junctions in reverse and in avalanche so that the space charge region extends along the entire channel length, the gate is set to the reference potential if the memory point does not have to be programmed and to a distinct potential if the memory point has to be programmed; and during the reading, circuitry is provided to detect a high or low impedance state between the gate and the well.