Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

Abstract: A generator circuit for a reference voltage independent of temperature variations uses a Brokaw cell biased by a current generator. The generator circuit includes a start-up circuit for delivering a current to the load of the generator using a transistor from the power-on instant until the switching on of the Brokaw cell and the consequent switching-off of the transistor. The circuit further includes a first field effect transistor having a gate coupled to a bandgap voltage node of the Brokaw cell and operatively connected in series with at least one diode between a biasing current generator of the start-up circuit and ground. The circuit also includes a second bipolar junction transistor having a base coupled to the power supply node of the Brokaw cell and operatively connected to a load resistance that is, in turn, connected to the supply rail and to the output transistor of the Brokaw cell for supplying current to the load during the start-up phase.

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.

Abstract: The invention relates to a self-regulated equalizer of the type which comprises a load circuit placed between first and second voltage references and having an input terminal which is connected to a modulated supply line, itself connected to the first voltage reference through a voltage step-up block placed between the first voltage reference and the modulated supply line and synchronized by a precharge enable signal received on a control terminal.

Abstract: A semiconductor device includes first through fourth pads and first through third external connection leads with the first external connection lead being a ground connection lead and the first and second pads being ground pads. First through fourth connection wires selectively connect the pads to the external connection leads. Additionally, a first ground line is connected to the first pad, a second ground line is connected to the second pad, a first protective diode connects the first ground line to the third pad, and a second protective diode connects the second ground line to the fourth pad. The first external connection lead is connected to the first pad via the first connection wire and to the second pad via the second connection wire, the third connection wire connects the third pad to the second external connection lead, and the fourth connection wire connects the fourth pad to the third external connection lead.

Abstract: A circuit for the generation of a high ramp voltage for the supply of voltage to a capacitive load, in particular a high voltage for the programming or erasure of at least one memory cell of a non-volatile memory, comprises floating-gate transistors as storage elements. This generation circuit comprises a P type load transistor connected by its source to the output of a voltage booster delivering a high direct and constant voltage (HIV), by its drain to the load, the high ramp voltage being available at this drain, and by its control gate to a control feedback circuit to control the load current. This circuit achieves automatic control over the slope of the high ramp voltage (Vpp). Application to the generation of a high ramp voltage whose slope is smaller than a critical slope and the maximum value is high.

Abstract: The video memory requisite of an MPEG decoder effecting a decompression of the I, P and optionally also of the B picture according to the MPEG compression algorithm and requiring the storing in respective buffers organized in said video memory of the respective MPEG-decompressed data, may be dynamically reduced by subsampling and recompressing according to a ADPCM algorithm of at least the data pertaining to the I and P pictures before coding and storing them in the respective buffers. Subsequently, the stored data are decoded, decompressed and upsampled for reconstructing blocks of pels to be sent to a macroblock-to-raster scan conversion circuit.

Abstract: A compensated voltage regulator of the type used in programming non-volatile memory cells of a memory cell matrix that is divided into sectors. The voltage regulator includes a comparator that is connected to a supply voltage. A first input terminal of the comparator is supplied a reference voltage, and a second input terminal is feedback connected to a program line. The control terminal of an output transistor is connected to an output terminal of the comparator, and a conduction terminal of the output transistor is connected to the memory cells by the program line. An output current is passed through a conduction terminal of the output transistor. Further, a compensation circuit is powered by the supply voltage. An input of the compensation circuit is connected to the output terminal of the comparator and to the output transistor, and an output of the compensation circuit is also connected to the output terminal of the comparator.

Abstract: A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage signal, and voltage comparator means for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises capacitive decoupling means for decoupling the voltage signal from the comparator means, and means for providing the capacitive decoupling means with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

Abstract: A method for locating possible defects on an opaque layer deposited on a production wafer of a semiconductor circuit, consisting in locally radiating an upper surface of the wafer by means of a laser, and detecting the occurrence of a current in a diode constituted by a PN junction placed under the opaque layer to be examined.

Abstract: A translator circuit for a drive circuit of a power transistor connected to an electric load. The translator circuit includes a first current generator placed between a supply voltage reference and an input terminal of the drive circuit, a controlled switch placed between the input terminal and a ground reference, and a second current generator interposed between the controlled switch and the ground reference. The translator circuit further includes a circuit leg in the form of a current mirror connected in parallel with the second current generator. The translator circuit avoids phenomena of false switching.

Abstract: An integrated image processing system includes an array of cells arranged in rows and columns. Each cell corresponds to a pixel of an image and includes a photosensitive element for detecting the luminous intensity of its respective pixel and for generating a value. A first switch controls the transfer of the value from a respective photosensitive element to the corresponding capacitor, which stores the value. A second switch couples each of the cells in parallel to a common line. A control circuit receives the values from each cell on the common line and generates a signal for regulating the switching time interval of the first switch.

Abstract: A voltage circuit generates a programming or erasure voltage for programming or erasing a floating-gate memory. The voltage generator circuit includes a charge pump to provide a pumped voltage and a shaping circuit to provide the programming or erasing voltage from the pumped voltage. A switching circuit enables the pumped voltage to reach a sufficient level before the shaping circuit generates the programming or erasure voltage.

Abstract: A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Abstract: A non-volatile integrated device having first and second dimensionally different polysilicon gate layers separated by an oxide layer for hot-carrier reliability. More specifically, the oxide and second polysilicon gate layer are selectively etched to form a second gate region over the first polysilicon gate layer that electrically contacts the first polysilicon gate in one direction and is isolated by the oxide in the other direction. Insulating sidewalls are formed over the first polysilicon gate layer regions that are not electrically contacted by the second gate layer to help isolate the second polysilicon gate and form an LDD structure within the substrate for the device.

Abstract: A fully differential voltage-current converter, comprising a differential operational amplifier which is supplied with a differential voltage to be converted into a current, a first transistor being fedback to a noninverting input of the amplifier, a second transistor being fedback to an inverting input of the amplifier, the second transistor having the opposite polarity with respect to the first transistor, a third transistor and a fourth transistor having mutually opposite polarities being connected between a supply voltage and ground and to the second transistor in order to force a current that flows through the second transistor to be equal to a current that flows through the first transistor, a gate terminal of the first transistor being connected to a gate terminal of the fourth transistor.

Abstract: An input structure for associative memories, including an array of elementary cells, a number of input lines, a number of output lines, a number of address lines, and a number of enable lines. Each elementary cell is formed by a D flip-flop having a data input coupled to one of the address lines and an enable input coupled to one of the enable lines, and by a switch coupled between an input line and an output line, and having a control input coupled to the output of a respective latch to selectively couple the respective input line and output line according to the data stored in the latch.

Abstract: A reading circuit comprises a current mirror circuit connected, at a first and a second output node, to the drain terminals of an array cell and of a reference cell; a comparator whose inputs are connected to the output nodes of the current mirror circuit; a ramp generator having an enabling input connected to the output of the comparator and an output connected to the control terminal of the reference cell. Biasing the gate terminal of the array cell to a constant voltage, when the currents flowing in the array cell and in the reference cell are equal, the value assumed by the ramp voltage is proportional to the threshold value of the array cell; at that time the comparator is triggered and discontinues the ramp increase, supplying as output the desired threshold value.

Abstract: An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.