Patents Assigned to STMicroelectronics A.A.
  • Area efficient EMI reduction technique for H-bridge current mode transmitter
    Patent number: 8410828
    Abstract: The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics Pvt Ltd.
    Inventor: Rajeev Jain
  • Passive contactless integrated circuit comprising a flag for monitoring an erase/programming voltage
    Patent number: 8410910
    Abstract: A passive contactless integrated circuit includes an electrically programmable non-volatile data memory (MEM), a charge accumulation booster circuit for supplying a high voltage necessary for writing data in the memory. The integrated circuit includes a volatile memory point for memorizing an indicator flag, and circuitry for modifying the value of the indicator flag when the high voltage reaches a critical threshold for the first time after activating the booster circuit.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics SA
    Inventors: David Naura, Christophe Moreaux, Ahmed Kari, Pierre Rizzo
  • Process and system for manufacturing an encapsulated semiconductor device
    Patent number: 8410593
    Abstract: A process for manufacturing a semiconductor device envisages the steps of: positioning a frame structure, provided with a supporting plate carrying a die of semiconductor material, within a molding cavity of a mold; and introducing encapsulating material within the molding cavity for the formation of a package, designed to encapsulate the die. The frame structure is further provided with a prolongation element mechanically coupled to the supporting plate inside the molding cavity and coming out of the molding cavity, and the process further envisages the steps of: controlling positioning of the supporting plate within the molding cavity with the aid of the prolongation element; and, during the step of introducing encapsulating material, separating and moving the prolongation element away from the supporting plate.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventor: Agatino Minotti
  • Method for manufacturing semiconductor chips from a semiconductor wafer
    Patent number: 8409967
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Patrick Hougron, Dominique Touzet, José Mendez
  • Tap time division multiplexing with scan test
    Patent number: 8412989
    Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics Limited
    Inventor: Robert Warren
  • Memory device with boost compensation
    Patent number: 8411518
    Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Dhori Kedar Janardan, Rakesh Kumar Sinha, Sachin Gulyani
  • PWM timer for power supply
    Patent number: 8412965
    Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Thomas L. Hopkins
  • Integrated microelectronic device with through-vias
    Patent number: 8410574
    Abstract: An integrated microelectronic device is formed from a substrate having a first side and a second side and including a doped active zone (2) in the first side of the substrate. A circuit component is situated in the doped active zone. A through silicon via extends between the second side and the first side, the via being electrically isolated from the substrate by an insulating layer. A buffer zone is situated between the insulating layer and the doped active zone. This buffer zone is positioned under a shallow trench isolation zone provided around the doped active zone. The buffer zone functions to reduce the electrical coupling between the through silicon via and the doped active zone.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Farcy, Maxime Rousseau
  • Fault injection detector in an integrated circuit
    Patent number: 8412988
    Abstract: A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a functional phase and a detection phase of the logic block, the isolation block applying, during the functional phase, the signal to be processed to at least one input of the logic block, and during the detection phase, a constant value to the input of the logic block; and a detection block adapted to monitor, during the detection phase, the state of the output signal of the logic block, and to generate an alert signal in case of any change in the state of the output signal.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Frédéric Bancel, Nicolas Berard
  • Non-deterministic number generation
    Patent number: 8411859
    Abstract: A method for determining the entropy of a noise source providing a bit flow, a method and a device for generating a bit flow, including parallelizing the bit flow to obtain first words over a first number of bits, applying to the successive words a compression function, and evaluating a second number of bits over which the compression function provides its results, the second number representing the number of useful bits in the first words.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Yannick Teglia, Pierre-Yvan Liardet
  • Electrical fuse device based on a phase-change memory element and corresponding programming method
    Patent number: 8410527
    Abstract: A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano, Roberto Bez
  • Digital predistorter for variable supply amplifier
    Patent number: 8411792
    Abstract: An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and including a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output of the power amplifier.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics S.A.
    Inventor: Vincent Pinon
  • Multi-channel inter base-station communication
    Patent number: 8411622
    Abstract: The invention relates to systems and methods for spectrum sharing and communication among several wireless communication networks with overlapping service areas (or cells); especially to Wireless Regional Area Networks (WRANs). Particular embodiments of the invention disclose using a conference channel to communicate between base stations. Other embodiments use slotted coexistence windows within frames to transmit and receive information, including for reserving transmission times within subsequent frames.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Wendong Hu
  • Error-locator-polynomial generation with erasure support
    Patent number: 8413023
    Abstract: A system and method for correcting errors in an ECC block using erasure-identification data when generating an error-locator polynomial. In an embodiment, a ECC decoding method, uses “erasure” data indicative of bits of data that are unable to be deciphered by a decoder. Such a method may use an Berlekamp-Massey algorithm that receives two polynomials as inputs; a first polynomial indicative of erasure location in the stream of bits and a syndrome polynomial indicative of all bits as initially determined. The Berlekamp-Massey algorithm may use the erasure identification information to more easily decipher the overall codeword when faced with a error-filled codeword.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics, Inc.
    Inventors: Vincent Brendan Ashe, Hakan C. Ozdemir, Razmik Karabed, Richard Barndt
  • Method for designing masks used to form electronic components
    Patent number: 8413082
    Abstract: A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Julia Castellan
  • Circuit integrating a tunable antenna with a standing wave rate correction
    Patent number: 8412121
    Abstract: An integrated electronic radio-frequency transceiver circuit, including: at least one terminal intended to receive a signal to be transmitted or to transmit a received signal; at least one planar antenna, with a settable resonance frequency; at least one bidirectional coupler having a primary line interposed between the terminal and the antenna and having the respective terminals of a secondary line providing data representative of the transmitted power and of the power reflected on the primary line side; at least one detector of the transmitted power and of the reflected power; and a circuit for selecting the resonance frequency of the antenna according to the ratio between the transmitted power and the reflected power.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Benoît Bonnet, François Dupont
  • Integrated directional coupler
    Patent number: 8410864
    Abstract: A coupler including: a first conductive line intended to convey a signal to be transmitted between first and second terminals; a second conductive line, coupled to the first one and having one end intended to provide, on a third terminal, data relative to a signal reflected on the second terminal; and an inductive and/or capacitive impedance matching circuit, interposed between the other end of the second line and a fourth terminal of the coupler.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Sylvain Charley, François Dupont, Hilal Ezzeddine
  • Pointing and control device and method for a computer system
    Patent number: 8411030
    Abstract: A pointing and control device for a computer system, the device having a body that can be maneuvered by a user; and an inertial sensor fixed to the body for supplying first signals correlated to the orientation of the body with respect to a gravitational field acting on the inertial sensor. The device moreover includes a magnetometer fixed to the body for supplying second signals correlated to the orientation of the body with respect to the Earth's magnetic field acting on the magnetometer and processing modules for determining an orientation of the body in an absolute reference system, fixed with respect to the Earth's magnetic field and gravitational field on the basis of the first signals and second signals.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Pasolini, Paolo Bendiscioli, Francesco Vocali, Fabio Biganzoli
  • Method and device for checking the integrity of a logic signal, in particular a clock signal
    Patent number: 8412996
    Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics SA
    Inventors: Frederic Bancel, Nicolas Berard, Philippe Roquelaure
  • MOS transistor with a settable threshold
    Patent number: 8410539
    Abstract: A MOS transistor comprising a conductive extension of its source region, insulated from its substrate, and partially extending under its channel.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascale Mazoyer, Germain Bossu