Abstract: A capacitive touch sensor includes horizontal lines vertical lines. Switching circuitry is coupled to the horizontal and vertical lines of the capacitive touch sensor. The switching circuitry is operable in a first mode to configure the horizontal lines as receive lines and the vertical lines as transmit lines for making a cross-capacitance measurement. In one implementation, the switching circuit is further operable in a second mode to configure the horizontal lines as transmit lines and the vertical lines as receive lines for making an additional cross-capacitance measurement. In another implementation, the switching circuit is further operable in a second mode to configure the vertical lines for making a self capacitance measurement. The various capacitance measurements from the first and second modes are algorithmically combined to obtain a total capacitance measurement having a reduced noise component.

Abstract: An embodiment of a method for channel estimation for an Orthogonal Frequency Division Multiplexing communication system, including estimating a Time Domain Least Squares channel impulse response having a given maximum number of L taps based on a channel covariance matrix Q, and for each tap l=1, . . . , L a respective channel impulse response in the time-domain ?l, wherein the channel impulse responses in the time-domain are grouped as a channel impulse response vector in the time domain ?. Specifically, an updated channel-impulse-response vector in the time domain {tilde over (h)} is determined by computing for each tap l the solution of the following system: Q1:l, 1:l{tilde over (h)}l×1=?1:l, wherein the updated channel-impulse-response vector in the time domain {tilde over (h)} is computed recursively via a Levinson Durbin algorithm.

Abstract: A digital input buffer and method. The input buffer includes a voltage regulator configured for operating in weak inversion and outputting a regulated potential, an inverter having as its power source the regulated potential and configured for receiving an input signal, a first latch having its input coupled to the inverter input, and a second latch having its input coupled to the inverter's output, having its output coupled to the first latch's enable input, and having its enable input coupled to the first latch's output. A first latch output signal from the first latch output and a second latch output signal from the second latch output enable switching the first latch output signal to the complement of the input signal and switching the second latch output signal to that of the input signal.

Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.

Abstract: An embodiment of a method for reducing chroma noise in digital image data and of a corresponding image processor. Chrominance components are subjected to low-pass filtering. The strength of the low-pass filtering is modulated in accordance with the dynamic range of the luminance signal and the dynamic range of each of the two chrominance signals in order to avoid color bleeding at image-object edges. Moreover, the low-pass filtering is selectively applied to pixels with similar luminance and chrominance values only. A combination of down-sampling and up-sampling units is employed so that comparatively small filter kernels may be used for removing chroma noise with low spatial frequency.

Abstract: The disclosure relates to a method for testing an integrated circuit, comprising in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage, the first test voltage being set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down, the second test voltage being set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: An integrated microelectromechanical structure is provided with: a driving mass, anchored to a substrate via elastic anchorage elements and moved in a plane with a driving movement; and a first sensing mass, suspended inside, and coupled to, the driving mass via elastic supporting elements so as to be fixed with respect to the driving mass in the driving movement and to perform a detection movement of rotation out of the plane in response to a first angular velocity; the elastic anchorage elements and the elastic supporting elements cause the detection movement to be decoupled from the driving movement. The elastic supporting elements are coupled to the first sensing mass at an end portion thereof, and the axis of rotation of the detection movement extends, within the first sensing mass, only through the end portion.

Abstract: A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars.

Abstract: A method for manufacturing a silicide layer in a hole formed across the entire thickness of a layer of a material deposited on a silicon layer, including: a first step of bombarding of the hole with particles to sputter the silicon at the bottom of the hole and deposit sputtered silicon on lateral walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; a second step of bombarding of the hole with particles to sputter the silicon precursor at the bottom of the hole and deposit sputtered precursor on the internal walls of the hole; a second step of deposition in the hole of a layer of silicide precursor; and an anneal step to form a silicide layer in the hole.

Abstract: The invention relates to a method of determining a zero-bias error of a gyroscope, an apparatus for determining a zero-bias error of a gyroscope and a system including the apparatus. The method includes the steps of: a. obtaining a set of outputs of the gyroscope; b. determining a dispersion degree of the outputs; c. determining whether the dispersion degree satisfies a predetermined condition and performing the step of d or e based upon a result of the determination; and d. determining an average of the outputs as the zero-bias error of the gyroscope when the dispersion degree satisfies the predetermined condition; or e. obtaining another set of outputs of the gyroscope and repeating performing the steps of b to c on the another set of outputs when the dispersion degree does not satisfy the predetermined condition.

Abstract: A system and method is capable of performing a Low Density Parity Check (LDPC) coding operation on-the-fly without using a generator matrix. The system and method includes an input configured to receive data and an output configured to output a plurality of codewords. The system and method also includes a processor coupled between the input and the output. The processor is configured to encode the received data and produce the plurality of codewords using a plurality of parity bits. The processor creates the plurality of parity bits on-the-fly using a portion of an LDPC matrix and a protograph matrix.

Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract: Systems and methods are disclosed herein for a motion detection system for video signal processing that includes a luminance motion detector, a chroma motion detector, and a smoothness detector. These systems and methods may also include a phase motion detector, a baseband YC separation circuitry for video signal processing, a chip for video signal processing, and a video signal processing system used in an electronic article.

Abstract: A transmission band of an analog signal including successive symbols to be transmitted is notched, where each symbol includes sub-carriers to be modulated. In particular, in each symbol the sub-carriers corresponding to a part of the transmission band to be notched are suppressed. In addition, in each symbol a chosen part of the remaining sub-carriers to be modulated is also suppressed.

Abstract: A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, wherein a ratio between data representative of a voltage across an oscillating circuit of the transponder and obtained for two pairs of inductive and capacitive values of this oscillating circuit is compared with one or several thresholds, the two pairs of values preserving a tuning of the oscillating circuit to a same frequency.

Abstract: The waveform of the signal varies according to the distance at which the signal was emitted, and several correlation signals are defined and correspond respectively to at least part of several sampled waveforms of the signal respectively emitted at several distances of different values so that the sum of the maxima of intercorrelations performed respectively between the various correlation signals and the various sampled waveforms is substantially constant over an interval including all the values of the distances. The correlation processing includes several elementary correlation processings respectively performed with the correlation signals and each delivering initial correlation values, as well as a summation of the homologous initial correlation values respectively delivered by the elementary correlation processings so as to obtain the correlation values.

Abstract: Systems and methods are for implementing a NSV2SV converter that converts a non-scalable video signal to a scalable video signal. In an implementation, a non-scalable video signal encoded in H.264/AVC standard is decoded and segmented into spatial data and motion data. The spatial data is resized into a desired resolution by down-sampling the spatial data. The motion data is also resized in every layer, except in the top layer, of a scalable video coding (SVC) encoder by using an appropriate measure. Further, the motion data is refined based on the resized spatial data in every layer of the SVC encoder. The refined motion data and the down-sampled spatial data are then transformed and entropy encoded in the SVC standard in every layer. The SVC encoded output from every layer is multiplexed to produce a scalable video signal.

Abstract: A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width.