Abstract: Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.

Abstract: A thermoelectric generator including, between first and second walls delimiting a tightly closed space, a layer of a piezoelectric material connected to output terminals; a plurality of openings crossing the piezoelectric layer and emerging into first and second cavities close to the first and second walls; and in the tight space, drops of a liquid, the first wall being capable of being in contact with a hot source having a temperature greater than the evaporation temperature of the liquid and the second wall being capable of being in contact with a cold source having a temperature smaller than the evaporation temperature of the liquid.

Abstract: A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Abstract: A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage.

Abstract: A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.

Abstract: A signal processor for processing a digital input signal including samples sampled at a sampling frequency, the signal processor comprising a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency; first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency; decimation circuitry arranged to decimate the first signal and the shifted second signal; and processing circuitry arranged to process the decimated first and second signals.

Abstract: A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

Abstract: A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract: A distributed differential coupler, including a first conductive line and two second conductive lines coupled to the first one, each second conductive line including two conductive sections electrically in series, their respective junctions points being intended to be grounded.

Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.

Abstract: A circuit includes a comparator having input terminals configured to be coupled across a drive transistor adapted to drive a phase of a motor. The comparator senses a drive current of the motor phase, said sensed drive current represented by a periodic signal whose period is indicative of motor speed. A motor speed calculation circuit receives the periodic signal and processes the periodic signal to determine a speed of the motor.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: In one or more embodiments, the disclosure relates to a method of setting a photolithography exposure machine, comprising: forming on a photolithography mask test patterns and circuit patterns, transferring the patterns to a resin layer covering a wafer, measuring a critical dimension of each test pattern transferred, and determining a focus setting error value of the photolithography machine from the measure of the critical dimension of each pattern, the test patterns formed on the mask comprising a first reference test pattern and a second test pattern forming for a photon beam emitted by the photolithography machine and going through the mask, an optical path having a length different from an optical path formed by the first test pattern and the circuit patterns formed on the mask.

Abstract: An embodiment of the invention relates to a method for transmission by ultra-wide-band pulses of digital data formed with a flow of information elements, this method comprising at least one operation including sequentially encoding the information elements by modulating an oscillating signal In order to avoid the use of a bandpass filter, the oscillating signal is modulated in amplitude depending on the identity or dissimilarity of each information element relative to the preceding information element.

Abstract: A graphic module wherein, given a curve P(x,y)=P(x(t), y(t)) between two points P0(x,y)=P0(x(t0), y(t0)) and P1(x,y)=P1(x(t1), y(t1), in the screen coordinates, a calculating circuit computes a curve mid-point Phalf(x,y)=Phalf(x(thalf), y(thalf)), where thalf=(t0+t1)/2 on the curve, computes a segment mid-point PM(x,y)=(P0(x,y)+P1(x,y))/2 on segment P0P1, computes a distance function d between the curve mid-point and the segment mid-point, and, given two thresholds THR0 and THR1, with THR0<=THR1, if d<THR0, it generates line segment P0P1, and if THR0<=d<THR1, it generates two line segments P0Phalf and PhalfP1 if d>=THR1, it repeats the previous steps for the curve portions from P0 to Phalf and from Phalf to P1.

Abstract: A system and method for providing a constant current source driver for a light emitting diode string. The converter includes a current sensor that derives feedback signal corresponding to a peak current through the light emitting diode string. The feedback signal is used by a controller to vary a duty cycle of the controller to regulate the average current. The controller is operable to regulate the average current as the number of light emitting diodes is increased and/or decreased.

Abstract: The addition of high throughput capability elements to beacon frames and peer link action frames in wireless mesh networks enable the utilization of desirable features without further modifications to the network. Rules can be established for high throughput mesh point protection in a mesh network, Space-time Block Code (STBC) operations and 20/40 MHz operation selections. However, features such as PSMP (power save multi-poll) and PCO (phased coexistence operations) are barred from implementation to prevent collisions.

Abstract: A substrate is provided with electrical connection pads on a front face and on a rear face, the front pads and rear pads being selectively connected via a network passing through the substrate. A peripheral edge of the substrate is mounted on a rigid annular frame and the rearm face secured to a suction table. A layer of a dielectric sealant containing electrically conductive particles is deposited on the front face and front pads of the substrate. Integrated-circuit chips are positioned on the front face to flatten the layer of dielectric sealant, the included electrically conductive particles making electrical connection between pads of the integrated-circuit and the front pads of the substrate. The resulting assembly in then encapsulated in a block of encapsulating material positioned on top of the front face of the substrate. The block is then diced in order to obtain a plurality of semiconductor packages.

Abstract: A method of processing digital images by transforming a set of pixels from a three-dimensional space to a normalized two-dimensional space, determining a membership class and membership class level of each pixel in the set of pixels, and selectively modifying colors of pixels in the set of pixels based on the determined membership classes and membership class levels.