Abstract: A wireless data transmitter including: a data modulator adapted to modulate a data signal based on a frequency signal; and at least one antenna adapted to wirelessly transmit the modulated data signal and the frequency signal independently.
Type:
Application
Filed:
June 7, 2012
Publication date:
December 13, 2012
Applicants:
Universite de Lille 1, STMicroelectronics S.A.
Inventors:
Christophe Loyez, Samuel Foulon, Sébastien Pruvost, Nathalie Rolland
Abstract: A method includes coupling two conducting rods between terminals of a battery cell of a battery having several branches coupled in parallel, each branch having several battery cells coupled in series. A force tending to squeeze the rods against each other is applied, with the rods being held apart from each other using an insulating block. At least one operating state signal of the cell is monitored, and the insulating block is removed based on the monitoring, allowing the rods to come into electrical contact and short-circuit the battery cell.
Abstract: The disclosure relates to a method of manufacturing vibratory elements, comprising forming on a substrate a multilayer structure by an integrated circuit manufacturing method, the multilayer structure comprising an element susceptible of vibrating when it is subjected to an electrical signal, and electrodes for transmitting an electrical signal to the vibratory element, the vibratory element comprising a mechanical coupling face that is able to transmit to control element vibrations perceptible by a user.
Type:
Application
Filed:
June 6, 2012
Publication date:
December 13, 2012
Applicants:
STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA
Abstract: The invention concerns a circuit for multi-standard wireless RF transmission comprising: input circuitry (302 to 314) for generating a transmission signal (IT(t), QT(t)) based on an input data signal (I, Q); a power amplifier (316) adapted to amplify said transmission signal to provide an output signal (S(t)) for transmission via at least one antenna; and feedback circuitry (320 to 340) comprising at least one variable low-pass filter (334, 336) for generating a feedback signal (IFB, QFB) based on said output signal, wherein said input circuitry further comprises pre-distortion circuitry (302) adapted to modify said input data signal (I, Q) based on said feedback signal.
Type:
Application
Filed:
November 18, 2011
Publication date:
December 13, 2012
Applicant:
STMicroelectronics SA
Inventors:
Nicholas Delaunay, Eric Kerherve, Nathalie Deltimple, Didier Belot
Abstract: The distribution of the service period (SP) and contention-based period (CBP) scheduling information in the data transfer time (DTT) of a beacon interval (BI) defined under the WGA Draft Specification 0.8 is selectively scheduled to optimize channel access contention. STAs in a single antenna scope or groups of STAs in multiple antennas scopes is allocated to different CBPs to decrease collisions. Simultaneous CBPs is further allocated to STAs in multiple antennas scopes where STAs have peer-to-peer traffic with other STAs in the same antenna group during part of the CBP when the personal PCP/AP is unavailable to that antenna group resulting in an increase in network throughput.
Abstract: A battery powering a propulsion engine of a vehicle, is controlled by determining state data representative of the operation and wear of the battery, authenticating state data using an encryption method, and transmitting authenticated state data to an on-board computer of the vehicle for display.
Abstract: A method for stereo audio perceptual encoding of an input signal includes masking threshold estimation and bit allocation. The masking threshold estimation and bit allocation are performed once every two encoding processes. Another method for stereo audio perceptual encoding of an input signal includes performing a time-to-frequency transformation, performing a quantization, performing a bitstream formatting to produce an output stream, and performing a psychoacoustics analysis. The psychoacoustics analysis includes masking threshold estimation on a first of every two successive frames of the input signal.
Type:
Grant
Filed:
August 22, 2006
Date of Patent:
December 11, 2012
Assignee:
STMicroelectronics Asia Pacific PTE., Ltd.
Abstract: A structure for protecting an integrated circuit against electrostatic discharges, comprising an assembly of identical cells, each of which is connected to a terminal forming a pad of the circuit, a first supply rail, or a second supply rail, the cells forming between any two of said terminals an assembly of four alternated layers of different conductivity types.
Type:
Grant
Filed:
April 14, 2010
Date of Patent:
December 11, 2012
Assignee:
STMicroelectronics SA
Inventors:
Philippe Galy, Christophe Entringer, Johan Bourgeat
Abstract: A process for transmitting a message between a first electronic device and a second electronic device of an energy distribution network is described. The process includes generating, by the first electronic device, a first data encryption key identifying the second electronic device on the basis of a main data encryption key and an identification code of the second electronic device. The process further includes generating, by the first electronic device and the second electronic device, a communication key on the basis of said first data encryption key and a reference datum.
Abstract: The invention provides for the encoding of surround sound produced by any coincident microphone techniques with coincident-to-virtual microphone signal matrixing. An encoding scheme provides significantly lower computational demand, by deriving the spatial parameters and output downmixes from the coincident microphone array signals and the coincident-to-surround channel-coefficients matrix, instead of the multi-channel signals.
Type:
Grant
Filed:
March 16, 2009
Date of Patent:
December 11, 2012
Assignee:
STMicroelectronics Asia Pacific Pte. Ltd.
Abstract: An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node.
Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.
Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.
Abstract: The broadcasting of audio contents by two loudspeakers is controlled by delivering a first audio content to the two loudspeakers and a further processing in which an auxiliary audio content is received. A second audio content is formed by temporally delaying the auxiliary audio content with a delay dependent on the spacing between the loudspeakers and on a distance between a first loudspeaker and a spot located in front of this first loudspeaker. The second audio content is delivered to the first loudspeaker. A third audio content is formed by inverting the auxiliary audio content. The third audio content is then delivered to the second loudspeaker.
Abstract: A switching power supply for supplying a load requiring a controlled current includes a PFC pre-regulator for receiving an input voltage and providing an output voltage, and a DC-DC switching converter for receiving at input the voltage output by the pre-regulator and for providing at output a supply voltage of said load. The switching DC-DC converter operates at a fixed and constant operating frequency, is a resonant converter and includes an LLC resonant circuit.
Abstract: The quality of music output from audio systems is improved by simulating the effect of low frequency signals in the human ear. This thus allows listeners to perceive the lower frequency signals, even though the speakers may be incapable of providing such low frequency outputs. Method and systems provided for processing enhancing bass effect in audio signals. Said method and systems result in the bass enhancement being computationally less intensive. The bass effect enhancement techniques described are based on the response of sine and cosine transfer functions and on the directional independence of low frequency components. The human ear is unable to resolve directions from low frequency components. The bass effect enhancement technique alternatively is based on response of an exponential transfer function.
Type:
Grant
Filed:
March 28, 2011
Date of Patent:
December 11, 2012
Assignee:
STMicroelectronics Asia Pacific Pte. Ltd.
Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.
Abstract: At least three metal-oxide semiconductor transistors with different threshold voltages are formed in and above corresponding first, second and third parts of a semiconductor substrate. The second transistor has a lower threshold voltage than the second transistor, and the third transistor has a lower threshold voltage than the second transistor. The gate oxide layers for the three transistors are formed as follows: a first oxide layer having a first thickness is formed above the first, second and third parts. The first oxide layer above the second part is etched and a second oxide layer having a second thickness smaller than the first thickness is formed. The first oxide layer above the third part is etched and a third oxide layer having a third thickness smaller than the second thickness is formed. The second and the third oxide layers are then nitrided to form first and second oxy-nitride layers.
Abstract: A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers.
Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.